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10095 Commits

Author SHA1 Message Date
clairexen 9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop 
Avoid generating wires for function args which are constant
 2020-07-26 21:34:55 +02:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Marcelina Kościelnicka bd959d5d9e async2sync: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka c9251eb26b memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 557f81cb49 proc_dlatch: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 31d6107521 pmux2shift: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 4d9105ccb0 wreduce: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 7b1a4fc1e6 techmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 9e72be3ae8 shregmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 522f367db3 abc: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 336b8c7786 dffinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 1c8483b7dd zinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka e98382f6e2 dfflegalize: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka abe4e9e607 clk2fflogic: Support all FF types. 2020-07-24 03:19:48 +02:00
Marcelina Kościelnicka 0c6d0d4b5d satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
Marcelina Kościelnicka dafe04d559 Add utility module for representing flip-flops. 2020-07-23 23:39:46 +02:00
Marcelina Kościelnicka eae2edf3e4 memory_dff: recognize more dff cells 2020-07-23 20:55:28 +02:00
Marcelina Kościelnicka 022af4f0ca Add utility module for dealing with init attributes. 2020-07-23 20:49:48 +02:00
clairexen c0ad522cf6
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname 
techmap: Add _TECHMAP_CELLNAME_ special parameter.
 2020-07-23 18:39:42 +02:00
clairexen 02583ad504
Merge pull request #2294 from Ravenslofty/intel_alm_timings 
intel_alm: add additional ABC9 timings
 2020-07-23 18:21:20 +02:00
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Keith Rothman 819f1d8c20 Remove EXPLICIT_CARRY logic. 
The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-07-23 00:56:09 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
 2020-07-21 15:00:54 +02:00
clairexen 57af8499df
Merge pull request #2215 from boqwxp/qbfsat-solver-options 
qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands
 2020-07-21 14:43:33 +02:00
Alberto Gonzalez 42fb75c570
smtio: Emit `mode: start` options before `set-logic` command and any other options after it. 
Refer to the SMT-LIB specification, section 4.1.7.  According to the spec, some options can only be specified in `start` mode.  Once the solver sees `set-logic`, it moves to `assert` mode.
 2020-07-20 22:09:44 +00:00
Alberto Gonzalez 654864658f
smtio: Add support for parsing `yosys-smt2-solver-option` info statements. 2020-07-20 21:54:56 +00:00
Alberto Gonzalez 2f786fcfac
qbfsat: Add `-solver-option` option. 2020-07-20 21:54:56 +00:00
Alberto Gonzalez f037985337
smt2: Add `-solver-option` option. 2020-07-20 21:54:56 +00:00
clairexen 856d40973d
Merge pull request #2282 from YosysHQ/claire/satunsat 
Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
 2020-07-20 23:06:36 +02:00
Marcelina Kościelnicka 3cb401db8c celltypes: Fix EN port name for some FF types. 2020-07-20 23:04:10 +02:00
Claire Wolf a207cb362c Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-20 19:35:32 +02:00
clairexen be6638e55b
Merge pull request #2276 from YosysHQ/mwk/satgen-cc 
satgen: Move importCell out of the header.
 2020-07-20 15:23:14 +02:00
Marcelina Kościelnicka 85a1bb17ed satgen: Move importCell out of the header. 
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
 2020-07-19 00:17:02 +02:00
Miodrag Milanović eed05953f8
Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix 
sf2: Emit CLKINT even if -clkbuf not passed
 2020-07-17 15:05:46 +02:00
Marcelina Kościelnicka 1b95b0e570 sf2: Emit CLKINT even if -clkbuf not passed 
This restores pre #2229 behavior.
 2020-07-17 15:01:47 +02:00
Miodrag Milanović 10bc0967e2
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix 
anlogic: Fix FF mapping.
 2020-07-17 14:39:31 +02:00
Marcelina Kościelnicka a4f7777e9d anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
clairexen 9a5d6e1789
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs 
sf2: replace sf2_iobs with {clkbuf,iopad}map
 2020-07-16 18:33:56 +02:00
clairexen f3d7e9a1df
Merge pull request #2273 from whitequark/write-verilog-always-star-initial 
verilog_backend: in non-SV mode, add a trigger for `always @*`
 2020-07-16 18:30:50 +02:00
clairexen c49344b262
Merge pull request #2272 from whitequark/write-verilog-sv 
verilog_backend: add `-sv` option, make `-o <filename>.sv` work
 2020-07-16 18:28:24 +02:00
Miodrag Milanović 910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic 
anlogic: Use dfflegalize.
 2020-07-16 18:07:58 +02:00
Miodrag Milanović b74eb598bc
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf 
efinix: Nuke efinix_gbuf in favor of clkbufmap.
 2020-07-16 18:07:41 +02:00
whitequark 128522f173 verilog_backend: in non-SV mode, add a trigger for `always @*`. 
This commit only affects translation of RTLIL processes (for which
there is limited support).

Due to the event-driven nature of Verilog, processes like

    reg x;
    always @*
        x <= 1;

may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:

    reg init = 0;
    reg x;
    always @* begin
        if (init) begin end
        x <= 1;
    end

Fixes #2271.
 2020-07-16 11:30:14 +00:00
whitequark d9f680b236 verilog_backend: add `-sv` option, make `-o <filename>.sv` work. 
See #2271.
 2020-07-16 10:44:08 +00:00
whitequark a87e338381
Merge pull request #2270 from whitequark/cxxrtl-fix-typo 
cxxrtl: fix typo
 2020-07-16 09:48:10 +00:00
whitequark cb757b28b4
Merge pull request #2269 from YosysHQ/claire/bisonwall 
Use "bison -Wall -Werror" for verilog front-end
 2020-07-15 19:20:33 +00:00
Claire Wolf 51ee0b683f Treat all bison warnings as errors in verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:57:31 +02:00
Claire Wolf 7a79843cc3 Use %precedence in verilog_parser.y 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:54:28 +02:00
Claire Wolf 24540291c7 Fix bison warnings for missing %empty 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:50:59 +02:00
Claire Wolf 1f4e452609 Run bison with -Wall for verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:49:36 +02:00