yosys

Author	SHA1	Message	Date
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys\|synthesis) comment support	2013-11-20 11:44:09 +01:00
Johann Glaser	f352205635	fixed Verilog parser filename and line numbering issue with include files	2013-08-21 09:20:59 +02:00
Johann Glaser	6c4cbc03c2	Added support for notif0/notif1 primitives	2013-08-20 11:23:59 +02:00
Clifford Wolf	8656b1c08f	Added support for bufif0/bufif1 primitives	2013-08-19 19:50:04 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	4b311b7b99	Further improved and extended xsthammer	2013-06-11 19:49:35 +02:00
Clifford Wolf	b56e06d2f5	Added support for verilog === operator	2013-05-07 14:35:40 +02:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00