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4,349 Commits 75 Branches 48 Tags 61 MiB
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4349 Commits

Author SHA1 Message Date
Clifford Wolf 00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00
Clifford Wolf e8da3ea7b6 Fixed another bug found using vloghammer 2013-07-07 16:49:30 +02:00
Clifford Wolf eff68560a2 Fixed AST_CONSTANT node generation 2013-07-07 15:40:26 +02:00
Clifford Wolf 52d21a63ca Removed tests/xsthammer 
This test is now available as 'vloghammer' in a seperate repository:
https://github.com/cliffordwolf/VlogHammer
 2013-07-07 13:01:15 +02:00
Clifford Wolf cf885c4a28 Added opt_clean -purge option 2013-07-07 12:59:30 +02:00
Clifford Wolf 0c0197cf45 Fixed handling of $eq and $ne in opt_const 2013-07-07 12:59:00 +02:00
Clifford Wolf 92a5961fd3 Fixed vivado related xsthammer bugs 2013-07-05 19:33:42 +02:00
Clifford Wolf 940f838dae Various improvements in xsthammer report generator 2013-07-05 16:04:02 +02:00
Clifford Wolf 3fd37061bf Added work-around to isim bug in xsthammer report script 2013-07-05 15:29:03 +02:00
Clifford Wolf f519297da9 Fixed gcc warnings in ezminisat 2013-07-05 15:00:20 +02:00
Clifford Wolf 238ff14810 Added CARRY4 Xilinx cell to xsthammer cell lib 2013-07-05 14:46:33 +02:00
Clifford Wolf 45105faf25 Added xsthammer report generator 2013-07-05 14:46:06 +02:00
Clifford Wolf cd33db25d1 Improved xsthammer quartus support 2013-07-04 21:26:49 +02:00
Clifford Wolf 14c84c111b Added Altera Cyclon III cell library to xsthammer 2013-07-04 14:50:03 +02:00
Clifford Wolf a4fd3cde8c Documentation updates 2013-07-04 14:17:25 +02:00
Clifford Wolf 56432a920f Added defparam support to Verilog/AST frontend 2013-07-04 14:12:33 +02:00
Clifford Wolf 3b294b3912 Added QMAKE makefile variable 2013-07-03 23:54:43 +02:00
Clifford Wolf be1fca3428 Added Altera Quartus support to xsthammer 2013-07-03 20:40:54 +02:00
Clifford Wolf 28539541ed Progress in xsthammer 2013-07-03 11:19:18 +02:00
Clifford Wolf a5fe2565b7 Added vivado support to xsthammer 2013-06-26 12:34:06 +02:00
Clifford Wolf 101491132f Added SAT support for -all/-max with -verify 2013-06-23 13:28:30 +02:00
Clifford Wolf 46b177eb8a Merge branch 'master' of github.com:cliffordwolf/yosys 2013-06-20 12:49:28 +02:00
Clifford Wolf 8fbb5b6240 Added timout functionality to SAT solver 2013-06-20 12:49:10 +02:00
Clifford Wolf a6aeb3dbf0 Added renaming of wires and cells to "rename" command 2013-06-19 16:55:43 +02:00
Clifford Wolf 21e38bed98 Added "eval" pass 2013-06-19 09:30:37 +02:00
Clifford Wolf a046a302f0 Fixed build with clang 2013-06-18 19:54:33 +02:00
Clifford Wolf 48aa72ae8f Added splitnets command 2013-06-18 17:11:36 +02:00
Clifford Wolf 6971c4db62 Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API 2013-06-18 17:11:13 +02:00
Clifford Wolf 5cf04f33fa Added more stuff to xsthammer, found first xst bug 2013-06-17 11:30:25 +02:00
Clifford Wolf c09b66b2a1 Added support for "assign" statements in abc vlparse 2013-06-15 13:50:38 +02:00
Clifford Wolf 6ef8c6fb8a Added ternary op and concat op to xsthammer 2013-06-15 11:00:34 +02:00
Clifford Wolf 6d7b5f9064 Fixed even more ConstEval bugs found using xsthammer 2013-06-14 17:50:26 +02:00
Clifford Wolf 30db70b1ba Added consteval testing to xsthammer and fixed bugs 2013-06-13 19:51:13 +02:00
Clifford Wolf 7f6c83a853 More xsthammer improvements (using xst 14.5 now) 2013-06-13 17:23:51 +02:00
Clifford Wolf 0c6ffc4c65 More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
Clifford Wolf b1d39aa865 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-06-12 19:31:17 +02:00
Clifford Wolf bf2c149329 Another fix for a bug found using xsthammer 2013-06-12 19:09:14 +02:00
Clifford Wolf a42dd4549b Added "scatter" command 2013-06-12 14:41:33 +02:00
Clifford Wolf 49293a182d Renamed yosys-show temp files to be dot-files in the users home directory 2013-06-12 10:42:59 +02:00
Clifford Wolf 1bee82ae2d Fixed gcc build (c++11 stuff in ezSAT) 2013-06-12 10:18:01 +02:00
Clifford Wolf 4b311b7b99 Further improved and extended xsthammer 2013-06-11 19:49:35 +02:00
Clifford Wolf 8ce99fa686 More xsthammer improvements 2013-06-10 21:07:22 +02:00
Clifford Wolf 7f3f25841e More sign-extension related fixes 2013-06-10 21:04:04 +02:00
Clifford Wolf a5c30183b5 Sign-extension related fixes in SatGen and AST frontend 2013-06-10 17:10:06 +02:00
Clifford Wolf 9026511821 Progress xsthammer scripts 2013-06-10 16:17:09 +02:00
Clifford Wolf 7d790febb0 Improvements and fixes in SAT code 2013-06-10 16:09:29 +02:00
Clifford Wolf 15ff4cc63b Added history file read/write to driver 2013-06-10 15:42:52 +02:00
Clifford Wolf a6370ce857 Progress in xsthammer: working proof for cell models 2013-06-10 14:02:11 +02:00
Clifford Wolf 59dd02baa2 Fixes and improvements in AST const folding 2013-06-10 13:56:03 +02:00
Clifford Wolf db98a18edb Enabled AST/Verilog front-end optimizations per default 2013-06-10 13:19:04 +02:00