95241c8f4d
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v ,
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(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
2018-08-20 00:08:08 +03:00
28cfc75a90
A few minor enhancements to specify block parsing.
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Just remember specify blocks are parsed but ignored.
2018-08-15 20:14:52 +03:00
ce3dc3e01d
Merge pull request #605 from mmicko/master
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Changes for MXE configuration in order to compile
2018-08-15 19:12:38 +02:00
a5136c768b
Changes for MXE configuration in order to compile
2018-08-15 19:08:45 +02:00
ed32760d4a
Merge pull request #573 from cr1901/msys-64
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Add support for 64-bit builds using msys2 environment, use msys-provided `libpthread`.
2018-08-15 14:20:10 +02:00
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error
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Fix remaining log_file_error(); emit dependent file references in new…
2018-08-15 14:01:34 +02:00
dfc0c8ffc8
Merge pull request #576 from cr1901/no-resource
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Gate POSIX-only signals and resource module to only run on POSIX Pyth…
2018-08-15 14:00:19 +02:00
d70830a1be
Merge pull request #592 from japm48/master
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fix basys3 example
2018-08-15 13:37:25 +02:00
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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Detect illegal port declaration, e.g input/output/inout keyword must …
2018-08-15 13:14:23 +02:00
1dd156f516
Fix use of signed integers in JSON back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-14 23:31:25 +02:00
2353d28ff2
Merge pull request #602 from litghost/add_eblif_extension
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Map .eblif extension as blif.
2018-08-14 12:47:41 +02:00
80d7e007ff
Map .eblif extension as blif.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-13 14:02:53 -07:00
93efbd5d15
Fixed use of char array for string in blifparse error handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-08 19:41:47 +02:00
b210e9d293
Merge pull request #596 from litghost/extend_blif_parser
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#565 Add BLIF parsing support for .conn and .cname
2018-08-08 19:39:23 +02:00
219f1e9fc9
Report error reason on same line as syntax error.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-08 10:22:55 -07:00
7b48da0bfc
Merge pull request #600 from jpathy/patch-1
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Use `realpath`
2018-08-06 10:44:21 +02:00
63f4cc38eb
Merge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotes
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readme: Fix formatting of a keyword
2018-08-06 10:41:53 +02:00
7db05b2cc1
Use `realpath`
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Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
2018-08-06 06:51:07 +00:00
da53206cd4
readme: Fix formatting of a keyword
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Single quotes were used instead of backticks leading to
incorrect formatting.
2018-08-06 13:33:02 +09:00
475c2af812
Use log_warning which does not immediately terminate.
2018-08-03 08:05:45 -07:00
f42d6a9c93
Add BLIF parsing support for .conn and .cname
2018-08-02 14:36:56 -07:00
beedaa5856
fix basys3 example
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Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.
Added `open_hw` needed for programming.
2018-07-22 22:29:31 +02:00
e275692e84
Verific: Produce errors for instantiating unknown module
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Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 18:44:05 +02:00
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
b50fe1e3e9
Upodate ABC to git rev ae6716b
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 14:35:32 +02:00
ab700ef215
Add missing -lz to MXE build
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 14:28:45 +02:00
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
3101b9b8c9
Fix remaining log_file_error(); emit dependent file references in new line.
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There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
2018-07-20 18:52:52 -07:00
323f6f6f60
Merge pull request #586 from hzeller/more-sourcepos-logging
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Convert more log_error() to log_file_error() where possible.
2018-07-20 19:22:59 +02:00
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
1de07eeee2
Merge pull request #585 from hzeller/use-file-warning-error
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Use log_file_warning(), log_file_error() functions
2018-07-20 17:46:06 +02:00
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
bf68e9a94a
Merge pull request #584 from hzeller/provide-source-location-logging
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Provide source-location logging.
2018-07-20 16:36:06 +02:00
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
87aef8f0cc
Add async2sync pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-19 15:31:12 +02:00
65234d4b24
Fix handling of eventually properties in verific importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-17 12:43:30 +02:00
5041ed2f7d
Fix verific -vlog-incdir and -vlog-libdir handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 18:47:42 +02:00
3b79a2e3dc
Merge pull request #581 from daveshah1/ecp5
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Adding ECP5 synthesis target
2018-07-16 16:58:14 +02:00
f897af626d
Fix "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 16:48:09 +02:00
3a3558acce
ecp5: Fixing miscellaneous sim model issues
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:56:12 +02:00
ee68b4d963
Merge branch 'master' of github.com:YosysHQ/yosys
2018-07-16 15:32:38 +02:00
f39b897545
Add "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 15:32:26 +02:00
e9ef077266
ecp5: Fixing 'X' issues with LUT simulation models
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:20:34 +02:00
b2c62ff8ef
ecp5: ECP5 synthesis fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 14:33:13 +02:00
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
241429abac
ecp5: Add DRAM match rule
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:25:52 +02:00
4a60bc83ab
ecp5: Cells and mappings fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:14:08 +02:00
b0fea67cc6
ecp5: Fixing arith_map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:49:59 +02:00
Udi Finkelstein
Clifford Wolf
Miodrag Milanovic
litghost
jpathy
Konrad Beckmann
japm48
Henner Zeller
David Shah