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12913 Commits

Author SHA1 Message Date
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanović ec4af6af2f
Merge pull request #3216 from YosysHQ/claire/simstuff 
Co-simulation improvements and fixes
 2022-02-28 08:19:54 +01:00
Miodrag Milanovic 9571acc0bf Support extended aiw format 2022-02-27 16:37:40 +01:00
Miodrag Milanovic fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Claire Xenia Wolf ca261d3c28 Experimental sim changes 2022-02-25 16:02:06 +01:00
github-actions[bot] 08c771078f Bump version 2022-02-25 01:04:22 +00:00
YRabbit 22d9bbb308 gowin: Remove unnecessary attributes 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-24 05:38:33 +01:00
YRabbit 9b3cd4f0d8 gowin: Add support for true differential output 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-24 05:38:33 +01:00
Anton Blanchard 89300b2dca abc: Fix {I} and {P} substitution 
We were searching for {D} after the first match of {I} or {P}.
 2022-02-23 18:54:28 +11:00
N. Engelhardt dc739362c7 print cell name for properties in yosys-smtbmc 2022-02-22 17:00:10 +01:00
Claire Xen a41c1df76f
Merge pull request #3211 from YosysHQ/micko/witness 
Add support for AIGER witness files in "sim" command
 2022-02-22 16:22:06 +01:00
Claire Xen ac294ed419
Merge pull request #3197 from YosysHQ/claire/smtbmcfix 
Add a bit of flexibilty re AIG witness trace length to smtbmc.py
 2022-02-22 15:26:22 +01:00
R 2d3a337795 json: Add help message for `signed` field 2022-02-21 21:59:25 -08:00
github-actions[bot] 286caa09bd Bump version 2022-02-22 00:59:35 +00:00
Miodrag Milanović d0b72e75d9
Merge pull request #3203 from YosysHQ/micko/sim_ff 
Simulation for various FF types
 2022-02-21 17:57:44 +01:00
Marcelina Kościelnicka d0f4d0b153 ecp5: Do not use specify in generate in cells_sim.v. 2022-02-21 17:52:31 +01:00
Miodrag Milanovic fd3f08753a Fix handling of ce_over_srst 2022-02-21 16:36:12 +01:00
N. Engelhardt 8fd1b06249 fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
Claire Xenia Wolf 1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-18 16:27:41 +01:00
Miodrag Milanovic 5f918803de Changed error message 2022-02-18 15:06:49 +01:00
Miodrag Milanovic 41754b4207 Added AIGER witness file co simulation 2022-02-18 15:04:02 +01:00
Miodrag Milanovic 13a5c28459 simplify logic of handling flip-flops and latches 2022-02-18 09:17:36 +01:00
Miodrag Milanovic 61752b255f Review cleanup 2022-02-17 17:18:36 +01:00
Miodrag Milanovic 29293a57bb Remove quotes if any from attribute 2022-02-16 19:10:13 +01:00
Miodrag Milanovic 21baf48e04 test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
Miodrag Milanovic 271ac28b41 Added test cases 2022-02-16 13:27:59 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
github-actions[bot] 1586000048 Bump version 2022-02-16 01:01:23 +00:00
Miodrag Milanović c9a32c0d92
Merge pull request #3204 from YosysHQ/claire/update-abc 
Bump ABC version
 2022-02-15 20:51:54 +01:00
Miodrag Milanovic 3bae2705fc Bump ABC version 2022-02-15 18:44:05 +01:00
github-actions[bot] 426f89fc6f Bump version 2022-02-15 01:05:31 +00:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy 68c67c40ec
Fix access to whole sub-structs (#3086) 
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-02-14 14:34:20 +01:00
github-actions[bot] 59738c09be Bump version 2022-02-13 01:02:04 +00:00
Marcelina Kościelnicka 3a62fa0c97 gowin: Add remaining block RAM blackboxes. 2022-02-12 11:48:57 +01:00
github-actions[bot] 1772a1e98e Bump version 2022-02-12 01:01:05 +00:00
Zachary Snow 15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Claire Xen ca876e7c12
Merge pull request #2376 from nmoroze/clk2ff-better-names 
clk2fflogic: nice names for autogenerated signals
 2022-02-11 17:30:32 +01:00
Claire Xenia Wolf 30eb7f8665 Add a bit of flexibilty re trace length when processing aiger witnesses in smtbmc.py 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-11 17:24:49 +01:00
Miodrag Milanović fc7d78f071
Merge pull request #3164 from zachjs/fix-ast-warn 
fix dumpAst() compilation warning
 2022-02-11 16:43:35 +01:00
Claire Xen 49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Claire Xen e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86 7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Lofty 5ac32ea68c abc9: add flow3mfs script 2022-02-10 18:28:35 +00:00
github-actions[bot] c8903e7053 Bump version 2022-02-10 00:58:51 +00:00
Miodrag Milanović a08fff9c0f
Merge pull request #3193 from YosysHQ/micko/verific_f 
Add ability to override verilog mode for verific -f  command
 2022-02-09 12:41:26 +01:00
Miodrag Milanovic 2cef48bf2c Add ability to override verilog mode for verific -f command 2022-02-09 09:19:25 +01:00
Marcelina Kościelnicka f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka ac2bb70b52 ecp5: Fix DPR16X4 sim model. 2022-02-09 09:02:13 +01:00