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12973 Commits

Author SHA1 Message Date
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder 1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files 
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates 
This is required for compatibility with non-multiclock formal semantics.
 2023-01-11 18:07:16 +01:00
Jannis Harder 9c6198a827 sim: Internal API to set $initstate 
This is not yet added to any of the simulation drivers.
 2023-01-11 18:07:16 +01:00
Jannis Harder 44b26d5c6d sim: Emit used memory addresses as signals to output traces 
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
 2023-01-11 18:07:16 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef 
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
 2023-01-11 18:07:16 +01:00
Jannis Harder 673ad561b8 smt2: Treat bweqx as xnor 
Without x-bits they are equivalent
 2023-01-11 18:07:16 +01:00
Jannis Harder 62afe61779 smt2: Directly implement bwmux instead of using bwmuxmap 2023-01-11 18:07:16 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 2e3c08adc4
Merge pull request #3570 from YosysHQ/claire/eqystuff 
Various Changes for EQY
 2023-01-11 16:37:52 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
N. Engelhardt d742d063d4 remove template declaration that stops function from being used 2023-01-11 16:09:05 +01:00
N. Engelhardt 41ce00e82a
Merge pull request #3620 from YosysHQ/gcc48_remove 2023-01-11 16:05:56 +01:00
Miodrag Milanovic 4fc5207b1e Add deprecation info to changelog 2023-01-11 11:23:23 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
YRabbit d6a1e022e1 gowin: add a new type of PLL - PLLVR 
This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-01-11 11:41:29 +10:00
github-actions[bot] 7b476996df Bump version 2023-01-11 01:16:47 +00:00
Miodrag Milanović 2677569d48
Merge pull request #3616 from YosysHQ/register_error 
Display error instead of assertion when pass exists
 2023-01-10 11:38:57 +01:00
Miodrag Milanović 2b622258a2
Merge pull request #3615 from YosysHQ/qbfsat_cvc5 
qbfsat support for cvc5, fixes #3608
 2023-01-10 11:38:16 +01:00
Miodrag Milanovic 40282576b0 Display error instead of assertion when pass exists 2023-01-09 17:02:56 +01:00
Miodrag Milanovic e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
github-actions[bot] f2c689403a Bump version 2023-01-05 00:16:46 +00:00
gatecat 7bac1920b2 nexus: Fix BRAM write enable in PDP mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 17:59:36 +01:00
github-actions[bot] d3216593da Bump version 2023-01-04 00:16:03 +00:00
Miodrag Milanovic c34d308bbd Next dev cycle 2023-01-03 09:36:13 +01:00
Miodrag Milanovic e02b7f64bc Release version 0.25 2023-01-03 09:34:45 +01:00
github-actions[bot] a27a297ebc Bump version 2023-01-03 00:15:41 +00:00
Peter Gadfort 7971154e72 Merge branch 'master' into stat-json-area 2023-01-02 12:46:41 -05:00
Miodrag Milanović 583ab81670
Merge pull request #3606 from YosysHQ/fix_vs 
Remove cache
 2023-01-02 17:47:13 +01:00
Miodrag Milanovic a935752df6 Remove cache 2023-01-02 17:16:51 +01:00
N. Engelhardt fcd1c68ab7 add note to help about how to chain commands 2023-01-02 16:10:28 +01:00
Miodrag Milanović 257b41cd1f
Merge pull request #3577 from KrystalDelusion/deprecate_manual 
Deprecate manual
 2023-01-02 16:07:36 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output 
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
 2022-12-29 21:51:46 -05:00
Claire Xenia Wolf 029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-21 14:50:23 +01:00
Claire Xenia Wolf 1bc832a8e1 Allow non-unique modules without state in sim writeback-mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:43:02 +01:00
Claire Xenia Wolf a9072dc23c Small bugfix in uniquify pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:41:48 +01:00
Jannis Harder 3ebc50dee4
Merge pull request #3467 from jix/fix_cellarray_simplify 
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
 2022-12-19 16:05:13 +01:00
KrystalDelusion f2a4e5f1a0 Fixing other references to the manual 
And files that were in the directory.
 2022-12-19 10:42:21 +13:00
KrystalDelusion f33a21eea4 Removed manual from make clean 2022-12-19 10:10:34 +13:00
KrystalDelusion aeb40d4ddf Remove make targets for manual 
Leaves the clean, since presentation source is still directly buildable and cleanable.
 2022-12-19 10:08:40 +13:00
github-actions[bot] 69cbef9666 Bump version 2022-12-16 00:16:00 +00:00
Miodrag Milanović 76de4455e6
Merge pull request #3588 from YosysHQ/noblackbox 
respect noblackbox attribute in verific
 2022-12-15 09:08:18 +01:00
Miodrag Milanovic b867dee241 respect noblackbox attribute in verific 2022-12-15 08:17:53 +01:00
github-actions[bot] 5d893c4b03 Bump version 2022-12-13 00:17:31 +00:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code 
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
 2022-12-12 17:51:01 +01:00
Jannis Harder 2093cf07e4
Merge pull request #3581 from jix/formalff-error 
formalff: Proper error messages on async inputs for the -clk2ff mode
 2022-12-12 16:39:10 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-09 18:28:17 +01:00
Jannis Harder 967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode 2022-12-09 15:25:40 +01:00