riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,239 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

3239 Commits

Author SHA1 Message Date
Clifford Wolf 308a4b4a1b Bugfix in "hierarchy -check" 2016-11-02 20:09:57 +01:00
Clifford Wolf 4832faf5e9 Updated command reference in manual 2016-11-02 19:25:28 +01:00
Clifford Wolf 8e48685706 Changelog for Yosys 0.7 2016-11-02 18:53:30 +01:00
Clifford Wolf b63cace90f Added support for fsm_encoding="user" 2016-11-02 13:15:49 +01:00
Clifford Wolf 0c8e973d32 Added "fsm_expand -full" 2016-11-02 09:31:39 +01:00
Clifford Wolf 56e2bb88ae Some fixes in handling of signed arrays 2016-11-01 23:17:43 +01:00
Clifford Wolf 81bdf0ad0f iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
Clifford Wolf caa2fc62ef Adde "write_verilog -renameprefix -v" 2016-11-01 11:30:27 +01:00
Clifford Wolf 1e3c2bff72 Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
Clifford Wolf d9d38eeedb Bugfix in fsm_map for FSMs without reset state 2016-10-25 23:21:37 +02:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 3655d7fea7 Added "setparam -type" 2016-10-19 13:54:04 +02:00
Clifford Wolf 042b67f024 No limit for length of lines in BLIF front-end 2016-10-19 12:44:58 +02:00
Clifford Wolf 0b3885bbfd Merge pull request #250 from azonenberg/master 
Add support for more GreenPak cells (edge detector, delay, pattern generator)
 2016-10-19 11:37:04 +02:00
Andrew Zonenberg 1cca1563c6 Fixed typo in last commit 2016-10-18 20:46:49 -07:00
Andrew Zonenberg e78fa157a3 greenpak4: Added GP_PGEN cell definition 2016-10-18 20:42:44 -07:00
Andrew Zonenberg 091d32b563 Added GLITCH_FILTER parameter to GP_DELAY 2016-10-18 19:53:19 -07:00
Andrew Zonenberg a818472f0c greenpak4: added model for GP_EDGEDET block 2016-10-18 19:33:26 -07:00
Andrew Zonenberg 2effa497a3 Merge https://github.com/cliffordwolf/yosys 2016-10-18 19:29:25 -07:00
Clifford Wolf 281a977b39 Ignore L_pi nets in "yosys-smtbmc --cex" 2016-10-18 10:54:53 +02:00
Clifford Wolf 9e980a2bb0 Use init value "2" for all uninitialized FFs in BLIF back-end 2016-10-18 10:54:04 +02:00
Clifford Wolf 0bcc617a4f Added "yosys-smtbmc --cex <filename>" 2016-10-17 14:57:28 +02:00
Clifford Wolf 15fb56697a Bugfix in "miter -assert" handling of assumptions 2016-10-17 14:56:58 +02:00
Clifford Wolf 6425d34e73 Added clk2fflogic support for $dffsr and $dlatch 2016-10-17 13:28:55 +02:00
Andrew Zonenberg d6feb4b43e greenpak4: Changed parameters for GP_SYSRESET 2016-10-16 22:53:43 -07:00
Clifford Wolf 3a09d6bb65 Improvements and bugfixes in clk2fflogic 2016-10-16 23:03:29 +02:00
Clifford Wolf 189fbd4cf8 cleanup in write_smt2 log messages (-bv and -mem are now default) 2016-10-16 23:02:51 +02:00
Clifford Wolf 74702b04c2 Build fixes for VS 2015 2016-10-16 20:37:02 +02:00
Clifford Wolf fa535c0b00 Some minor build fixes for Visual C 2016-10-14 18:36:02 +02:00
Clifford Wolf e4c5ee9b89 Avoid using strcasecmp() 2016-10-14 18:20:36 +02:00
Clifford Wolf 7fc69b3095 Fixed version string for out-of-tree builds 2016-10-14 17:18:18 +02:00
Clifford Wolf 512f93f866 Added notes about some formal features to README 2016-10-14 15:39:33 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 2733994aeb Added clk2fflogic 2016-10-14 14:55:07 +02:00
Clifford Wolf 2ef454c3f5 Added opt_rmdff support for $ff cells 2016-10-14 13:02:36 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf ffbb4e992e Added MEMID handling to "flatten" pass 2016-10-14 10:36:37 +02:00
Clifford Wolf 09aeb9a2aa Merge branch 'master' of github.com:cliffordwolf/yosys 2016-10-14 09:36:40 +02:00
Clifford Wolf 3c42462aa1 Merge pull request #246 from set-soft/abc_external_ovr 
Allow to overwrite ABCEXTERNAL from the environment.
 2016-10-14 09:36:31 +02:00
Clifford Wolf 788e51164e Added YOSYS_VER_STR make variable 2016-10-14 09:35:18 +02:00
Salvador E. Tropea 80749f174c Ugh! extra patches got here, reverting 2016-10-13 17:57:09 -03:00
Salvador E. Tropea cc8f29a1e6 Allow to overwrite ABCEXTERNAL from the environment. 
In this way Debian scripts can define it as berkeley-abc from the shell.
 2016-10-13 17:51:14 -03:00
Salvador E. Tropea f263b175b5 Modified test target name (to test-all) 
As this target depends on external tools, and packagers run "make test",
I think the name should be less generic.
 2016-10-13 17:38:42 -03:00
Salvador E. Tropea 77ce8139a5 Added a new configuration variable GIT_REV_WHERE 
It determines from where we get the gits SHA1 value. By default is HEAD,
suitable for Clifford, but for Debian we can define it as upstream/master
 2016-10-13 17:34:15 -03:00
Clifford Wolf ee91350add Added "zinit" pass 2016-10-12 12:05:19 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 4a981a3bd8 Fixed "make test" for git head of iverilog 2016-10-11 12:12:32 +02:00
Clifford Wolf 59508c99b4 define PATH_MAX if not defined by limits.h 2016-10-11 12:12:09 +02:00
Clifford Wolf 11130d581d Merge branch 'master' of github.com:cliffordwolf/yosys 2016-10-11 03:58:27 +02:00