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14261 Commits

Author SHA1 Message Date
Catherine 43ddd89ba5 cxxrtl: fix `escape_c_string` hex literal fiasco. 
In C and C++, a `\x` escape sequence consumes as many hexadecimal digits
as there are available, so it is not composable with arbitrary alnum
characters afterwards. An octal escape sequence like `\000` always has
fixed width, avoiding an issue where `\x01c` and `\x1c` produce the same
string.
 2024-05-08 02:55:17 +00:00
Roland Coeurjoly 6f9507a16f Add pkg-config 2024-05-08 04:47:40 +02:00
Roland Coeurjoly 1c89e2ab92 Add nix flake and lock file. Add nix build step. Pending nix flake update step 2024-05-08 03:52:12 +02:00
Ethan Mahintorabi c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Catherine 7294d8b5af cxxrtl: fix close of invalid fd in spool destructor. 2024-05-08 00:46:10 +00:00
github-actions[bot] ce45011275 Bump version 2024-05-08 00:13:52 +00:00
Roland Coeurjoly 6d181c29ce Checking different cases for abc 2024-05-08 00:32:18 +02:00
Roland Coeurjoly fdbe8714c9 Check that abc is checkout out as a git repo 2024-05-08 00:32:18 +02:00
Roland Coeurjoly 67d4c8bba6 Use $< to refer to the first prerequisite listed in the rule 2024-05-08 00:32:18 +02:00
Roland Coeurjoly 09b9aa83c9 Add YosysHQ/abc as a submodule located in abc 2024-05-08 00:32:18 +02:00
Miodrag Milanović c9d87d5e7b
Merge pull request #4377 from jix/smtbmc-incremental-improvements 
smtbmc: Improvements for --incremental and .yw fixes
 2024-05-07 21:35:10 +02:00
N. Engelhardt 8735107c60
Merge pull request #4321 from YosysHQ/fix_read_verilog_defaults 
read_verilog: Add missing defaults for flags
 2024-05-07 21:11:42 +02:00
Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
Jannis Harder a52088b6af smtbmc: Improvements for --incremental and .yw fixes 
This extends the experimental incremental JSON API to allow arbitrary
smtlib subexpressions, defining smtlib constants and to allow access of
signals by their .yw path.

It also fixes a bug during .yw writing where values would be re-emitted
in later cycles if they have no newer defined value and a potential
crash when using --track-assumes.
 2024-05-07 17:57:37 +02:00
Miodrag Milanovic 71f2540cd8 docs conf.py change Release -> Version 2024-05-07 15:55:52 +02:00
Miodrag Milanovic b4034a881e Keep docs version in conf.py 2024-05-07 15:35:25 +02:00
Miodrag Milanović 90dd508156
Merge pull request #4372 from YosysHQ/krys/docs_version_number 
Docs: Set release to YOSYS_VER
 2024-05-07 09:15:51 +02:00
Krystine Sherwin 6eb49ee9e8
Makefile: Export YOSYS_VER only for make docs 2024-05-07 10:23:22 +12:00
Emil J 68c7fc4c91
Merge pull request #4300 from YosysHQ/cellmatch 
cellmatch: New pass for picking out standard cells automatically
 2024-05-06 15:12:37 +02:00
Krystine Sherwin fe27240b3a
Makefile: Export YOSYS_VER 2024-05-04 16:51:38 +12:00
Krystine Sherwin bb0be8c7a2
Docs: Set release to YOSYS_VER 
If building from read the docs, and the current build is "latest", add `-dev` to the version string.
Requires `YOSYS_VER` to be exported by .readthedocs.yaml.
 2024-05-04 16:51:29 +12:00
github-actions[bot] 0f9ee20ea2 Bump version 2024-05-04 00:16:00 +00:00
Emil J. Tywoniak 44b0fdc2bf bbox_derive: add assert and debug print 2024-05-03 20:43:01 +02:00
Emil J. Tywoniak e8c58a5528 bbox_derive: fix unininitialized memory UB when run with no named args 2024-05-03 20:41:42 +02:00
Martin Povišer 4c000d3aba Add new `bbox_derive` command for blackbox derivation 2024-05-03 20:39:11 +02:00
Emil J. Tywoniak e939182e68 cellmatch: add comments 2024-05-03 16:42:41 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to `$cellmatch` 2024-05-03 16:42:41 +02:00
Martin Povišer 913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Martin Povišer c0e68dcc4d cellmatch: Add debug print 2024-05-03 16:42:41 +02:00
Martin Povišer 6a9858cdad cellmatch: Delegate evaluation to `ConstEval` 2024-05-03 16:42:41 +02:00
Martin Povišer 86e1080f05 cellmatch: New pass 2024-05-03 16:42:41 +02:00
Emil J 2631c7e918
Merge pull request #4365 from widlarizer/techmap-chtype-test 
techmap: add dynamic cell type test
 2024-05-03 16:25:42 +02:00
Emil J. Tywoniak a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Martin Povišer 6ff4ecb2b4 techmap: Remove `techmap_chtype` from the result 2024-05-03 13:33:28 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
github-actions[bot] dd2195543b Bump version 2024-04-30 00:17:14 +00:00
Martin Povišer 640d6a5127
Merge pull request #4359 from georgerennie/aiger_parse_bug 
read_aiger: Fix incorrect read of binary Aiger without outputs
 2024-04-29 15:15:43 +02:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
Jason Wu f1672b2f14
Update Makefile 2024-04-29 10:16:22 +08:00
Jason Wu 374cd3966d export define marco to qtcreator.config 2024-04-29 10:04:34 +08:00
N. Engelhardt 34d9a7451e
Merge pull request #4333 from YosysHQ/fix_hierarchy_generate 
fix hierarchy -generate mode handling of cells
 2024-04-25 09:56:24 +02:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Krystine Sherwin f2ebc3f7b1
github: Add template for documentation issues 2024-04-25 09:39:23 +12:00
Martin Povišer cd1fb8b157
Merge pull request #4350 from jix/read_rtlil_performance 
rtlil: Add packed `extract` implementation for `SigSpec`
 2024-04-24 14:07:28 +02:00
github-actions[bot] cf02f86c28 Bump version 2024-04-24 00:16:06 +00:00
Martin Povišer 982a22da5e
Merge pull request #4351 from povik/bump-abc 
Bump abc
 2024-04-23 14:20:54 +02:00
Martin Povišer 67c7062fb8 Bump abc for a fix once more 2024-04-23 13:50:45 +02:00
Martin Povišer c167d9b76e Bump abc for one more fix 2024-04-23 11:41:20 +02:00