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Merge pull request #4321 from YosysHQ/fix_read_verilog_defaults
read_verilog: Add missing defaults for flags
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commit
8735107c60
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@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
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frontend_verilog_yydebug = false;
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sv_mode = false;
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formal_mode = false;
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noassert_mode = false;
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noassume_mode = false;
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norestrict_mode = false;
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assume_asserts_mode = false;
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assert_assumes_mode = false;
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lib_mode = false;
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specify_mode = false;
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default_nettype_wire = true;
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