yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	6c05badc43	New techmap default rules for $shr $sshr $shl $sshl	2014-07-30 18:49:12 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	973507d85b	Fixes for improved techmap of shifts with large B inputs	2014-03-06 13:33:12 +01:00
Clifford Wolf	8406e7f7b6	Strictly zero-extend unsigned A-inputs of shift operations in techmap	2014-03-06 12:15:44 +01:00
Clifford Wolf	d7f29bb23f	Improved techmap of shift with wide B inputs	2014-03-06 12:14:20 +01:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	bef17eeb10	Removed cases of trailing comma in stdcells.v	2014-01-18 15:36:17 +01:00
Clifford Wolf	b3b00f1bf4	Various small cleanups in stdcells.v techmap code	2013-12-31 15:41:40 +01:00
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	404b46674b	Fixed techmap of $reduce_xnor with multi-bit outputs	2013-11-07 00:58:06 +01:00
Clifford Wolf	b41740060b	Fixed techmap of $gt and $ge with multi-bit outputs	2013-11-06 22:59:45 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	0836a1f2ba	Bugfix in dffsr techmap rules	2013-10-18 13:24:44 +02:00
Clifford Wolf	8197169f8d	Added techmap rules for $sr, $dffsr and $dlatch	2013-10-18 12:29:21 +02:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00

18 Commits