Eddie Hung
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d365682a21
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Add aiger tests to make tests
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2019-02-19 15:25:47 -08:00 |
Eddie Hung
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ef1a1402bc
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Add a quick abc9 test
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2019-02-19 15:25:03 -08:00 |
Eddie Hung
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7b026c4bc3
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Same for ascii AIGERs too
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2019-02-19 15:15:50 -08:00 |
Eddie Hung
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d304882cba
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read_aiger to cope with non-unique POs
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2019-02-19 15:14:08 -08:00 |
Eddie Hung
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f9af902532
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Merge branch 'master' into xaig
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2019-02-19 14:20:04 -08:00 |
Eddie Hung
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92b60d5e42
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Merge branch 'master' into read_aiger
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2019-02-19 12:36:10 -08:00 |
Eddie Hung
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78873d5bbb
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Merge branch 'master' into read_aiger
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2019-02-19 12:33:22 -08:00 |
Eddie Hung
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2a8e5bf953
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Merge pull request #805 from eddiehung/dff_init
write_verilog to write initial statement for initial flop state
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2019-02-19 12:32:40 -08:00 |
Eddie Hung
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8158bc3f99
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abc9 to replace $_NOT_ with $lut
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2019-02-19 12:30:20 -08:00 |
Eddie Hung
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e79df5e70e
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read_aiger to create sane $lut names, and rename when renaming driving wire
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2019-02-19 12:27:50 -08:00 |
Eddie Hung
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0b1fc46ae3
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Add comment
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2019-02-19 10:24:55 -08:00 |
Eddie Hung
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54f719f446
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Get rid of boost dep, fix the FIXMEs for Win32?
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2019-02-19 10:19:53 -08:00 |
Eddie Hung
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843e7fc8a7
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Fix for using POSIX basename
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2019-02-19 09:02:37 -08:00 |
Clifford Wolf
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62493c91b2
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Add first draft of functional SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-19 14:47:27 +01:00 |
Eddie Hung
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8e1dbfac3a
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Missing OSX headers?
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2019-02-17 20:59:53 -08:00 |
Eddie Hung
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de1dc7947b
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Revert "Missing headers for Xcode?"
This reverts commit c23e3f0751 .
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2019-02-17 20:59:15 -08:00 |
Eddie Hung
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3af8d420c5
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Merge branch 'dff_init' into read_aiger
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2019-02-17 20:49:56 -08:00 |
Eddie Hung
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11480b4fa3
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Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf
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2019-02-17 12:18:12 -08:00 |
Eddie Hung
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3d3353e020
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Revert "Add INIT parameter to all ff/latch cells"
This reverts commit 742b4e01b4 .
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2019-02-17 12:11:52 -08:00 |
Eddie Hung
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9268a271fb
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read_aiger to ignore line after ands for ascii, not binary
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2019-02-17 12:07:14 -08:00 |
Eddie Hung
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430a7548bc
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One more merge conflict
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2019-02-17 11:50:55 -08:00 |
Eddie Hung
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144c5d4359
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Merge branch 'dff_init' into read_aiger
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2019-02-17 11:49:13 -08:00 |
Eddie Hung
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17cd5f759f
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Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-17 11:49:06 -08:00 |
Eddie Hung
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03a533d102
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Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-02-17 11:44:01 -08:00 |
Clifford Wolf
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5a853ed46c
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Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-17 15:35:48 +01:00 |
Clifford Wolf
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c06c062469
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Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
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2019-02-17 12:10:19 +01:00 |
Clifford Wolf
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e45f62b0c5
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Merge pull request #811 from ucb-bar/firrtlfixes
Update cells supported for verilog to FIRRTL conversion.
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2019-02-17 11:39:14 +01:00 |
Eddie Hung
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45d49d5d14
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Get rid of debugging stuff in abc9
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2019-02-16 22:25:22 -08:00 |
Eddie Hung
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82459c16c4
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In read_xaiger, do not construct ConstEval for every LUT
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2019-02-16 22:22:29 -08:00 |
Eddie Hung
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30f1204721
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Cleanup
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2019-02-16 22:22:17 -08:00 |
Eddie Hung
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f60cd4ff9b
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read_aiger to ignore output = input of same wire; also create new output for different wire
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2019-02-16 21:53:03 -08:00 |
Eddie Hung
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76c35f80f4
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Cleanup
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2019-02-16 21:09:48 -08:00 |
Eddie Hung
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6a57de9013
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write_xaiger to support non-bit cell connections, and cope with COs for -O
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2019-02-16 21:00:39 -08:00 |
Eddie Hung
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f853b2f3c1
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abc9 to write_aiger with -O option, and ignore dummy outputs
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2019-02-16 20:09:40 -08:00 |
Eddie Hung
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b9a305b85d
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write_aiger -O to write dummy output as __dummy_o__
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2019-02-16 20:08:59 -08:00 |
Eddie Hung
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d8c4d4e6c7
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abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
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2019-02-16 13:47:38 -08:00 |
Eddie Hung
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1a25ec4baa
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read_aiger to disable log_debug
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2019-02-16 13:45:51 -08:00 |
Eddie Hung
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e7c7ab8fc0
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expose command to not skip 'internal' wires beginning with '$'
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2019-02-16 13:45:17 -08:00 |
Eddie Hung
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8f36013fac
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read_xaiger() to use f.read() not readsome()
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2019-02-16 08:58:25 -08:00 |
Eddie Hung
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d4545d415b
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abc9 to cope with non-wideports, count cells properly
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2019-02-16 08:53:06 -08:00 |
Eddie Hung
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0c409e6d8c
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Tidy up write_xaiger
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2019-02-16 08:48:33 -08:00 |
Eddie Hung
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2c1655ae94
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write_aiger() to perform CI/CO post-processing and fix symbols
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2019-02-16 08:46:25 -08:00 |
Eddie Hung
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7523c87780
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read_aiger() to cope with constant outputs, mixed wideports, do cleaning
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2019-02-16 08:44:11 -08:00 |
Eddie Hung
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f8d0134598
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Move lookup inside if
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2019-02-15 15:23:26 -08:00 |
Eddie Hung
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486a270415
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Fixes needed for DFF circuits
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2019-02-15 15:22:18 -08:00 |
Eddie Hung
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a786ac4d53
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Refactor
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2019-02-15 13:00:13 -08:00 |
Eddie Hung
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914546efd9
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Cope with width != 1 when re-mapping cells
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2019-02-15 12:55:52 -08:00 |
Jim Lawson
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c245041bfe
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Removed unused variables, functions.
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2019-02-15 12:00:28 -08:00 |
Jim Lawson
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34153adef4
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Append (instead of over-writing) EXTRA_FLAGS
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2019-02-15 11:56:51 -08:00 |
Eddie Hung
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956ee545c5
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abc9 to stitch results with CI/CO properly
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2019-02-15 11:52:34 -08:00 |