76c4ee4ea5
techmap, flatten: remove dead options.
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After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
2020-06-04 00:02:12 +00:00
6ac54a74fe
flatten: split from techmap.
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Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
2020-06-03 15:34:03 +00:00
577859fbdb
Merge pull request #2104 from whitequark/simplify-techmap
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techmap: simplify
2020-06-03 12:45:02 +00:00
fb5b070e7e
techmap: remove dead variable. NFC.
2020-06-03 01:44:06 +00:00
0a74368bfc
techmap: use C++11 default member initializers. NFC.
2020-06-02 23:43:20 +00:00
f3e86bb32a
techmap: simplify.
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`rewrite_filename` is already called in `Frontend::extra_args`.
2020-06-02 23:43:20 +00:00
68d747f767
techmap: use +/techmap.v instead of an ad-hoc code generator.
2020-06-02 23:43:20 +00:00
4b3f48a7ec
Merge pull request #2102 from YosysHQ/tests_fix
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allow range for mux test
2020-06-02 17:13:08 +02:00
2ed045738b
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric
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Support asymmetric memories for verific frontend
2020-06-02 17:12:02 +02:00
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
71072d1945
Support asymmetric memories for verific frontend
2020-06-01 10:30:03 +02:00
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
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Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
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blackbox: use Module::makeblackbox() method
2020-05-30 08:59:20 -07:00
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout
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smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-30 15:04:51 +02:00
ea30465107
smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.
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Co-Authored-By: clairexen <claire@symbioticeda.com>
2020-05-29 21:33:00 +00:00
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
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Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control
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Restrict RTLIL::IdString to not contain whitespace or control chars
2020-05-29 16:31:44 +02:00
5874a14d65
Merge pull request #2017 from boqwxp/qbfsat-cvc4
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qbfsat: Add support for CVC4.
2020-05-29 16:23:10 +02:00
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices
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qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
2020-05-29 16:21:45 +02:00
626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
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ilang_lexer: fix check for out of range literal
2020-05-29 09:04:27 +00:00
13b2963ded
ilang_lexer: fix check for out of range literal.
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Commit ca70a104
2020-05-29 06:58:44 +00:00
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
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verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
efa7424fb9
Restrict RTLIL::IdString to not contain whitespace or control chars.
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This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
2020-05-29 06:43:18 +00:00
f88bef7672
Document division and modulo cells
2020-05-28 22:59:04 +02:00
c34cb90a20
Update CHANGELOG
2020-05-28 22:59:04 +02:00
7c89738382
Add comments for mod/div semantics to rtlil.h
2020-05-28 22:59:04 +02:00
6a2bac21d3
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
edd8ff2c07
Add flooring division operator
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The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
17163cf43a
Add flooring modulo operator
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The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo
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Fix small typos in documentation for hierarchy command
2020-05-28 10:49:14 +00:00
1158bbf7db
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs
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Add `printattrs` command to print attributes of currently selected objects.
2020-05-28 10:25:34 +00:00
2384a59e2a
Merge pull request #2051 from Xiretza/makefile-cd-warning
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Suppress warning during initial clone of ABC repo
2020-05-28 10:00:49 +00:00
736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master
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Add extmodule support to firrtl backend
2020-05-28 09:59:17 +00:00
2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl
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firrtl: Accept techmapped cell types in FIRRTL backend.
2020-05-28 09:42:58 +00:00
02bb52eef1
Merge pull request #2088 from rswarbrick/count-at
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Minor optimisation in Module::wire() and Module::cell()
2020-05-28 09:41:17 +00:00
fdca785eda
Merge pull request #2087 from rswarbrick/lex-warn
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Silence spurious warning in Verilog lexer when compiling with GCC
2020-05-28 09:41:04 +00:00
8a44a46806
Merge pull request #2086 from rswarbrick/sigbit
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Use default copy constructor for RTLIL::SigBit
2020-05-28 09:40:49 +00:00
5b62dbb0af
Merge pull request #2084 from rswarbrick/c_str
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Use c_str(), not str() for IdString/std::string == and != operators
2020-05-28 09:40:35 +00:00
5896ffd56f
printattrs: Simplify `get_indent_str()`.
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Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
2020-05-28 05:34:28 +00:00
f671c99cb8
printattrs: Refactor indentation string building for clarity.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 23:15:07 +00:00
6228b10c9f
printattrs: Add test.
2020-05-27 08:00:00 +00:00
e50e4ee285
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 08:00:00 +00:00
b8365547e9
misc: Add `printattrs` command.
2020-05-27 08:00:00 +00:00
b651352193
Merge pull request #2090 from whitequark/cxxrtl-fixes
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Minor fixes for CXXRTL
2020-05-26 22:18:14 +00:00
0bf6b164be
cxxrtl: make logging a little bit nicer.
2020-05-26 21:37:32 +00:00
e9c07e2bda
cxxrtl: add missing parts of commit 281c9685.
2020-05-26 21:34:20 +00:00
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
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The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
7ff306ccdb
Minor optimisation in Module::wire() and Module::cell()
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The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
2020-05-26 16:07:36 +01:00
whitequark
clairexen
Miodrag Milanovic
Eddie Hung
Alberto Gonzalez
Xiretza
Rupert Swarbrick