70c47690b3
Updating todo text and assorted fixes
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Fix #3905 by removing emoji (and move the comment into the if block for less ambiguity).
Adds `latexmk` to README.
Note that latexpdf doesn't seem to like `cmd:ref` links, possibly because the
reference location is inside a latex comment block, but I was under the
impression that there was a reference location in there previously which was
working fine. May be related to how the `cmd:def` block expands (or doesn't as
the case may be).
2023-08-28 10:09:43 +12:00
4f1cd66829
New structure headings
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Also adds a note to readme for installing pdflatex if it's missing.
2023-08-03 09:20:24 +12:00
0d5e9acd34
README.md: s/write_ilang/write_rtlil/
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It's my understanding write_ilang is deprecated so best no to mention it
in the README.
2023-07-10 12:57:05 +02:00
4b95fac139
Removing old manual from README.md
2022-12-08 05:51:07 +13:00
b9b5899cce
Remove docs dependency on yosys repo ( #3558 )
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* Copies guidelines files into docs/ for website
* Copying manual/CHAPTER_Prog for new docs
* Copying manual/APPNOTE_011... for new docs
Also adding faketime to list of packages for website build.
Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
2022-11-24 15:56:44 +01:00
a14dec79eb
Rst docs conversion ( #3496 )
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Rst docs conversion
2022-11-15 12:55:22 +01:00
5343911263
Mention smtlib2_module in README.md and CHANGELOG
2022-07-04 13:54:49 +02:00
15b4d05805
mention distributions' package manager
2022-01-17 12:49:32 +01:00
6483e691bc
mention tabby+oss cad suite in readme
2022-01-04 15:44:37 +01:00
e833c6a418
verilog: use derived module info to elaborate cell connections
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- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
2021-10-25 18:25:50 -07:00
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
d9ec35a526
split CodingReadme into multiple files
2021-03-22 19:16:25 +01:00
fbb346ea91
flatten: preserve original object names via hdlname attribute.
2020-06-08 20:19:41 +00:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
9b26a1fa89
README: explain how to do out-of-tree builds.
2020-04-24 23:27:43 +00:00
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
ed4fa19ba2
Update Copyright
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-16 16:28:25 +01:00
418c069561
License: bump year and add title
2020-03-14 16:46:07 +00:00
0f4c1906bb
Small fixes
2020-02-27 10:29:53 -08:00
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
577545488a
xilinx: use specify blocks in place of abc9_{arrival,required}
2020-02-27 10:17:29 -08:00
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
1c16311d10
update documentation for enums and typedefs
2020-02-17 04:42:55 -05:00
a7df492243
Add comment for macOS dependency install
2020-02-15 09:44:32 +01:00
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
0488492ad2
Update CHANGELOG and README
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:13:13 +00:00
e0bdf5d7a9
Fix typo
2020-01-27 12:30:39 -08:00
168c9d5871
Update README.md for (* abc9_required *)
2020-01-15 14:42:00 -08:00
ffd38cb5ea
Reword (* abc9_flop *) description
2020-01-06 09:03:18 -08:00
c40b1aae42
Restore abc9 -keepff
2020-01-01 08:34:43 -08:00
ece423415c
Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md
2019-12-30 14:24:58 -08:00
ff2645ce0b
Put specify/endspecify inside ``
2019-12-20 13:38:32 -08:00
2666482282
Update README.md :: abc_ -> abc9_
2019-12-11 16:38:43 -08:00
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
b60f32c6ec
Update CHANGELOG and README
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-22 12:46:19 +00:00
1746b6373b
Update CHANGELOG and README
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
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Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
71d355560e
Update README.md
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 17:20:29 +02:00
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
d87a6f6303
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:32:58 -07:00
9c4e1c6a8f
Format `-pwires`
2019-08-30 10:27:07 -07:00
c52db44f9a
Group abc_* attribute doc with other attributes
2019-08-29 12:13:52 -07:00
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Krystine Sherwin
Martin Povišer
KrystalDelusion
Jannis Harder
N. Engelhardt
Zachary Snow
Claire Xenia Wolf
whitequark
Peter Crozier
Claire Wolf
Waldir Pimenta
Eddie Hung
Claire Wolf
Jeff Wang
Miodrag Milanović
David Shah
Marcin Kościelnicki