Clifford Wolf
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2a9ad48eb6
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Added ENABLE_NDEBUG makefile options
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2015-01-24 12:16:46 +01:00 |
Clifford Wolf
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aad195b88c
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Added "dfflibmap -prepare" help
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2014-12-24 12:56:05 +01:00 |
Clifford Wolf
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35f5aa300f
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Added "dfflibmap -prepare"
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2014-12-24 12:19:20 +01:00 |
Clifford Wolf
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84ffe04075
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Fixed various VS warnings
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2014-10-18 15:20:38 +02:00 |
Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Clifford Wolf
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d148b0af0d
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Fixed inserting of Q-inverters in dfflibmap
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2014-08-27 19:44:12 +02:00 |
Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
Clifford Wolf
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b9bd22b8c8
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More cleanups related to RTLIL::IdString usage
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2014-08-02 13:19:57 +02:00 |
Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
Clifford Wolf
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91704a7853
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Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
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2014-03-11 14:24:24 +01:00 |
Clifford Wolf
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cdf0f10760
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Fixed dfflibmap for cell libraries with no set-reset-ff
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2014-02-15 16:34:12 +01:00 |
Clifford Wolf
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9a00980129
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renamed LibertyParer to LibertyParser
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2014-01-14 18:57:47 +01:00 |
Clifford Wolf
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334b0cc803
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Fixed dfflibmap for unused output ports
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2013-12-21 20:47:22 +01:00 |
Clifford Wolf
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8856cec308
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Now prefer smallest cells in dfflibmap
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2013-12-21 08:42:37 +01:00 |
Clifford Wolf
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1fb29050e5
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Cleanup of dfflibmap cellmap exploration code
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2013-12-20 14:21:18 +01:00 |
Clifford Wolf
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eaf7d9675d
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Further improved dfflibmap cellmap exploration
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2013-12-20 12:34:34 +01:00 |
Clifford Wolf
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404bcc2d1e
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Fixed dfflibmap endless-loop bug
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2013-12-20 12:13:51 +01:00 |
Clifford Wolf
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c904f5e197
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Prefer non-inverted clocks in dfflibmap
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2013-12-19 13:21:57 +01:00 |
Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
Clifford Wolf
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0efe16f118
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Added placeholder check to dfflibmap and cleaned up some other placeholder checks
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2013-10-31 12:27:07 +01:00 |
Clifford Wolf
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dd56004fc0
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Added support for sr flip-flops to dfflibmap
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2013-10-24 18:20:06 +02:00 |
Clifford Wolf
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b6db2d9b33
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Moved dfflibmap from passes/dfflibmap to passes/techmap
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2013-10-16 15:32:26 +02:00 |