David Shah
c2d7be140a
ecp5: Adding basic synth_ecp5 based on synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4
ecp5: Adding DFF maps
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:32:23 +02:00
Clifford Wolf
db4514944d
Merge pull request #580 from daveshah1/ice40_nx
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ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
2018-07-13 14:31:38 +02:00
David Shah
1def34f2a6
ecp5: Adding DRAM map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
William D. Jones
0caa62802c
Gate POSIX-only signals and resource module to only run on POSIX Python implementations.
2018-07-06 01:44:34 -04:00
Aman Goel
f0b1ec3e97
Merge branch 'YosysHQ-master'
2018-07-04 15:14:58 -04:00
Aman Goel
4d343fc1cd
Merging with official repo
2018-07-04 15:14:28 -04:00
Clifford Wolf
8b92ddb9d2
Fix verific eventually handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:24:58 +02:00
Clifford Wolf
0404cf61d5
Add verific support for eventually properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:21:04 +02:00
Clifford Wolf
ebf0f003d3
Add "verific -formal" and "read -formal"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 10:02:27 +02:00
Clifford Wolf
afedb2d03e
Add "read -sv -D" support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 23:58:15 +02:00
Clifford Wolf
07e616900c
Add "read -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 23:43:38 +02:00
Clifford Wolf
fe2ee833e1
Fix handling of signed memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 16:57:03 +02:00
William D. Jones
7e5801beed
Add support for 64-bit builds using msys2 environment.
2018-06-27 16:36:18 -04:00
William D. Jones
ee7164b879
Use msys2-provided pthreads instead of abc's.
2018-06-27 16:26:36 -04:00
Clifford Wolf
848c3c5c88
Add YOSYS_NOVERIFIC env variable for temporarily disabling verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-22 20:40:22 +02:00
Clifford Wolf
d412b17259
Add simplified "read" command, enable extnets in implicit Verific import
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-21 16:56:55 +02:00
Clifford Wolf
9e096b1512
Merge branch 'master' of github.com:YosysHQ/yosys
2018-06-20 23:45:26 +02:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
c1d6934663
Merge pull request #572 from q3k/q3k/fix-protobuf-build
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Fix protobuf build
2018-06-20 20:40:59 +02:00
Sergiusz Bazanski
1690dafde1
Fix protobuf build
2018-06-20 19:28:43 +01:00
Clifford Wolf
626b555244
Merge pull request #571 from q3k/q3k/protobuf-backend
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Add Protobuf backend
2018-06-19 15:02:04 +02:00
Serge Bazanski
53e9a1549c
Add Protobuf backend
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Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
2018-06-19 13:34:56 +01:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Clifford Wolf
25c5002f83
Merge pull request #570 from edcote/patch-4
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Include module name for area summary stats
2018-06-19 13:47:39 +02:00
Edmond Cote
d89560a0ba
Include module name for area summary stats
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The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
2018-06-18 17:29:01 -07:00
Clifford Wolf
0ff0ce4973
Bugfix in liberty parser (as suggested by aiju in #569 )
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-15 18:56:44 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Udi Finkelstein
8b7580b0a1
Detect illegal port declaration, e.g input/output/inout keyword must be the first.
2018-06-06 22:27:25 +03:00
Clifford Wolf
270c1814b5
Merge pull request #561 from udif/pr_skip_typo
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Fixed typo (sikp -> skip)
2018-06-06 11:57:41 +02:00
Udi Finkelstein
106af19b69
Fixed typo (sikp -> skip)
2018-06-05 22:41:27 +03:00
Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Udi Finkelstein
80d9d15f1c
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
Clifford Wolf
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
Clifford Wolf
f273291dfe
Add setundef -anyseq / -anyconst support to -undriven mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:57:28 +02:00
Clifford Wolf
4cd6d5556a
Add "setundef -anyconst"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:49:58 +02:00
Clifford Wolf
3ab79a231b
Bugfix in handling of array instances with empty ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-31 18:09:31 +02:00
Clifford Wolf
7f0548c16f
Update examples/cmos/counter.ys to use "synth" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 14:17:36 +02:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Clifford Wolf
a77e27ab15
Update ABC to git rev 6df1396
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:10:10 +02:00
Clifford Wolf
cee4b1e6bc
Disable memory_dff for initialized FFs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 17:16:15 +02:00
Clifford Wolf
74efafc1cf
Add some cleanup code to memory_nordff
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 16:42:06 +02:00
Clifford Wolf
9a946c207f
Add comment to VIPER #13453 work-around
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 13:36:35 +02:00
Clifford Wolf
001c9f1d45
Fix Verific handling of single-bit anyseq/anyconst wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-25 15:41:45 +02:00
Clifford Wolf
251562a491
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-24 18:13:38 +02:00
Clifford Wolf
4d645f0fce
Fix verific handling of anyconst/anyseq attributes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-24 17:07:06 +02:00
Clifford Wolf
a5f4b44745
Merge pull request #454 from rqou/emscripten-and-abc
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Add option to statically link abc; emscripten fixes
2018-05-19 08:42:45 +02:00