Clifford Wolf
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97ac77513f
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Bugfix in "setundef" pass
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2016-11-08 18:53:36 +01:00 |
Clifford Wolf
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84badc97b3
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Added examples/gowin/
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2016-11-07 12:55:56 +01:00 |
Clifford Wolf
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ef603c6fe1
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Implemented "scc -set_attr"
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2016-11-06 00:04:10 +01:00 |
Clifford Wolf
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914aa8a5d3
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Bugfix in "scc" command
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2016-11-06 00:03:35 +01:00 |
Clifford Wolf
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2874914bcb
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Fixed anonymous genblock object names
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2016-11-04 07:46:30 +01:00 |
Clifford Wolf
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3db2ac4e00
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Added hex constant support to write_verilog
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2016-11-03 12:13:23 +01:00 |
Clifford Wolf
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e3330fb98f
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We are now in 0.7+ development
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2016-11-03 10:31:51 +01:00 |
Clifford Wolf
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61f6811627
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Yosys 0.7
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2016-11-03 09:08:43 +01:00 |
Clifford Wolf
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308a4b4a1b
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Bugfix in "hierarchy -check"
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2016-11-02 20:09:57 +01:00 |
Clifford Wolf
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4832faf5e9
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Updated command reference in manual
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2016-11-02 19:25:28 +01:00 |
Clifford Wolf
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8e48685706
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Changelog for Yosys 0.7
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2016-11-02 18:53:30 +01:00 |
Clifford Wolf
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b63cace90f
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Added support for fsm_encoding="user"
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2016-11-02 13:15:49 +01:00 |
Clifford Wolf
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0c8e973d32
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Added "fsm_expand -full"
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2016-11-02 09:31:39 +01:00 |
Clifford Wolf
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56e2bb88ae
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Some fixes in handling of signed arrays
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2016-11-01 23:17:43 +01:00 |
Clifford Wolf
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81bdf0ad0f
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iCE40 flow is not experimental anymore
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2016-11-01 11:32:02 +01:00 |
Clifford Wolf
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cae5131bac
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Added initial version of "synth_gowin"
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2016-11-01 11:31:13 +01:00 |
Clifford Wolf
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caa2fc62ef
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Adde "write_verilog -renameprefix -v"
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2016-11-01 11:30:27 +01:00 |
Clifford Wolf
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1e3c2bff72
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Added support for (single-clock) transparent memories to bram tests
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2016-11-01 10:03:13 +01:00 |
Clifford Wolf
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d9d38eeedb
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Bugfix in fsm_map for FSMs without reset state
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2016-10-25 23:21:37 +02:00 |
Clifford Wolf
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aa72262330
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Added avail params to ilang format, check module params in 'hierarchy -check'
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2016-10-22 11:05:49 +02:00 |
Clifford Wolf
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3655d7fea7
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Added "setparam -type"
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2016-10-19 13:54:04 +02:00 |
Clifford Wolf
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042b67f024
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No limit for length of lines in BLIF front-end
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2016-10-19 12:44:58 +02:00 |
Clifford Wolf
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0b3885bbfd
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Merge pull request #250 from azonenberg/master
Add support for more GreenPak cells (edge detector, delay, pattern generator)
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2016-10-19 11:37:04 +02:00 |
Andrew Zonenberg
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1cca1563c6
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Fixed typo in last commit
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2016-10-18 20:46:49 -07:00 |
Andrew Zonenberg
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e78fa157a3
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greenpak4: Added GP_PGEN cell definition
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2016-10-18 20:42:44 -07:00 |
Andrew Zonenberg
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091d32b563
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Added GLITCH_FILTER parameter to GP_DELAY
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2016-10-18 19:53:19 -07:00 |
Andrew Zonenberg
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a818472f0c
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greenpak4: added model for GP_EDGEDET block
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2016-10-18 19:33:26 -07:00 |
Andrew Zonenberg
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2effa497a3
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Merge https://github.com/cliffordwolf/yosys
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2016-10-18 19:29:25 -07:00 |
Clifford Wolf
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281a977b39
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Ignore L_pi nets in "yosys-smtbmc --cex"
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2016-10-18 10:54:53 +02:00 |
Clifford Wolf
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9e980a2bb0
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Use init value "2" for all uninitialized FFs in BLIF back-end
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2016-10-18 10:54:04 +02:00 |
Clifford Wolf
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0bcc617a4f
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Added "yosys-smtbmc --cex <filename>"
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2016-10-17 14:57:28 +02:00 |
Clifford Wolf
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15fb56697a
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Bugfix in "miter -assert" handling of assumptions
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2016-10-17 14:56:58 +02:00 |
Clifford Wolf
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6425d34e73
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Added clk2fflogic support for $dffsr and $dlatch
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2016-10-17 13:28:55 +02:00 |
Andrew Zonenberg
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d6feb4b43e
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greenpak4: Changed parameters for GP_SYSRESET
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2016-10-16 22:53:43 -07:00 |
Clifford Wolf
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3a09d6bb65
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Improvements and bugfixes in clk2fflogic
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2016-10-16 23:03:29 +02:00 |
Clifford Wolf
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189fbd4cf8
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cleanup in write_smt2 log messages (-bv and -mem are now default)
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2016-10-16 23:02:51 +02:00 |
Clifford Wolf
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74702b04c2
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Build fixes for VS 2015
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2016-10-16 20:37:02 +02:00 |
Clifford Wolf
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fa535c0b00
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Some minor build fixes for Visual C
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2016-10-14 18:36:02 +02:00 |
Clifford Wolf
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e4c5ee9b89
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Avoid using strcasecmp()
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2016-10-14 18:20:36 +02:00 |
Clifford Wolf
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7fc69b3095
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Fixed version string for out-of-tree builds
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2016-10-14 17:18:18 +02:00 |
Clifford Wolf
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512f93f866
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Added notes about some formal features to README
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2016-10-14 15:39:33 +02:00 |
Clifford Wolf
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bdc316db50
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Added $anyseq cell type
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2016-10-14 15:24:03 +02:00 |
Clifford Wolf
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2733994aeb
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Added clk2fflogic
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2016-10-14 14:55:07 +02:00 |
Clifford Wolf
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2ef454c3f5
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Added opt_rmdff support for $ff cells
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2016-10-14 13:02:36 +02:00 |
Clifford Wolf
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53655d173b
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Added $global_clock verilog syntax support for creating $ff cells
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2016-10-14 12:33:56 +02:00 |
Clifford Wolf
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ffbb4e992e
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Added MEMID handling to "flatten" pass
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2016-10-14 10:36:37 +02:00 |
Clifford Wolf
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09aeb9a2aa
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-10-14 09:36:40 +02:00 |
Clifford Wolf
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3c42462aa1
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Merge pull request #246 from set-soft/abc_external_ovr
Allow to overwrite ABCEXTERNAL from the environment.
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2016-10-14 09:36:31 +02:00 |
Clifford Wolf
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788e51164e
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Added YOSYS_VER_STR make variable
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2016-10-14 09:35:18 +02:00 |
Salvador E. Tropea
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80749f174c
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Ugh! extra patches got here, reverting
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2016-10-13 17:57:09 -03:00 |