Commit Graph

6006 Commits

Author SHA1 Message Date
Eddie Hung 6bbd286e03 Error out if -abc9 and -retime specified 2019-07-10 12:47:48 -07:00
David Shah 27b27b8781 synth_ecp5: Fix typo in copyright header
Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 22:26:10 +01:00
Clifford Wolf cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 22:59:51 +02:00
Clifford Wolf 6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
write_verilog: fix placement of case attributes
2019-07-09 22:51:25 +02:00
Eddie Hung f604aa174e
Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc
Revert "Add "synth -keepdc" option"
2019-07-09 12:19:40 -07:00
whitequark 37bb6b5e96 write_verilog: fix placement of case attributes. NFC. 2019-07-09 19:14:03 +00:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung 00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Rename __builtin_bswap32 -> bswap32
2019-07-09 10:22:57 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Eddie Hung 5a0f2e43c7 Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
Clifford Wolf e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
A new proc_prune pass
2019-07-09 16:59:18 +02:00
Clifford Wolf 38e942507e
Merge pull request #1163 from whitequark/more-case-attrs
More support for case rule attributes
2019-07-09 16:57:16 +02:00
Clifford Wolf ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs
Allow attributes on individual switch cases in RTLIL
2019-07-09 16:56:29 +02:00
Clifford Wolf a429aedc0f
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Cleanup synth_xilinx SRL inference, make more consistent
2019-07-09 16:49:08 +02:00
whitequark 44bcb7a187 proc_prune: promote assigns to module connections when legal.
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark 5fe0ffe30f proc_prune: new pass.
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark f2fb958d44 bugpoint: add -assigns and -updates options. 2019-07-09 09:27:43 +00:00
whitequark f7a14a5678 proc_clean: add -quiet option.
This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
Eddie Hung 7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc
Add "synth -keepdc" option
2019-07-08 21:43:16 -07:00
Eddie Hung 7600ffe4bd Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-08 19:26:43 -07:00
Eddie Hung 41d7d9d24b Clarify script -scriptwire doc 2019-07-08 19:21:21 -07:00
Eddie Hung fccabd0943 Add synth -keepdc to CHANGELOG 2019-07-08 19:15:37 -07:00
Eddie Hung 37b58f4324 Clarify 'wreduce -keepdc' doc 2019-07-08 19:15:07 -07:00
Eddie Hung dd9771cbcd Add synth -keepdc option 2019-07-08 19:14:54 -07:00
Eddie Hung ede1ef61c5
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2
Add muxcover -mux2=cost option
2019-07-08 14:34:37 -07:00
David Shah 22334fea40
Merge pull request #1160 from ZirconiumX/cyclone_v
synth_intel: Warn about untested Quartus backend
2019-07-08 21:04:33 +01:00
Eddie Hung b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung 3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
whitequark 628437b01c verilog_backend: dump attributes on SwitchRule.
This appears to be an omission.
2019-07-08 15:11:29 +00:00
whitequark 48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
whitequark 55c1f40277 verilog_backend: dump attributes on CaseRule, as comments.
Attributes are not permitted in that position by Verilog grammar.
2019-07-08 12:48:50 +00:00
whitequark b1f400aeb8 genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Dan Ravensloft 4f798cda9d synth_intel: Warn about untested Quartus backend 2019-07-07 19:26:31 +01:00
Clifford Wolf 030483ffb9
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
Throw runtime exception when trying to convert inexistend C++ object to Python
2019-07-05 11:57:41 +02:00
Benedikt Tutzer 3a1a41bdb1 Throw runtime exception when trying to convert a c++-pointer to a
python-object in case the pointer is a nullptr to avoid a segfault.

Fixes #1090
2019-07-04 14:20:13 +02:00
Eddie Hung de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
write_xaiger to treat unknown cell connections as keep-s
2019-07-03 09:43:00 -07:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf 1f173210eb Fix tests/various/specify.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:25:05 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Clifford Wolf 224ad8fe33
Merge pull request #1154 from whitequark/manual-sync-always
manual: explain the purpose of `sync always`
2019-07-03 10:45:29 +02:00
Eddie Hung 10524064e9 write_xaiger to treat unknown cell connections as keep-s 2019-07-02 19:14:30 -07:00
Eddie Hung 9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung 8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire
Add "script -select [selection]" to allow commands to be taken from wires
2019-07-02 10:20:42 -07:00
whitequark 9251c000e8 manual: explain the purpose of `sync always`. 2019-07-02 17:10:13 +00:00
Eddie Hung 810f8c5dbd Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup 2019-07-02 09:21:02 -07:00
David Shah 0447794c51
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
memory_dff: Fix checking of feedback mux input when more than one mux
2019-07-02 16:47:54 +01:00
Eddie Hung 81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00