riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,607 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

10607 Commits

Author SHA1 Message Date
Clifford Wolf 020a35d11e Removed date from auto-generated passes/techmap/stdcells.inc 2013-03-18 07:32:33 +01:00
Clifford Wolf 52914c2e68 Fixed abc eeror handling 2013-03-18 07:31:59 +01:00
Johann Glaser 3b8ebd694d add header to autogenerated file on its origin 2013-03-18 07:28:31 +01:00
Johann Glaser cd8008bda0 fixed typos 2013-03-18 07:28:31 +01:00
Clifford Wolf ba3793b642 Fixed strerrno vs. strerror types in ABC pass 2013-03-17 09:28:58 +01:00
Clifford Wolf 0133a98b73 Merge branch 'hansi' 2013-03-17 09:18:00 +01:00
Clifford Wolf 1390de4b74 Cleaned up ABC file/io error handling 2013-03-17 09:17:18 +01:00
Clifford Wolf e6cbeb5b16 Set execute bit on tests/openmsp430/run-synth.sh for real 2013-03-17 09:10:09 +01:00
Johann Glaser 0cb4a5936f added error checking at execution of ABC 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:03 +01:00
Johann Glaser fb494d4dd7 corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:02 +01:00
Johann Glaser a6f004e6f8 set executable flags to run-synth.sh, added .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:02 +01:00
Johann Glaser 3cfbc18601 added ckeck for Icarus Verilog, otherwise the tests are silently stopped 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:15 +01:00
Johann Glaser bcae4aae6e corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:14 +01:00
Clifford Wolf 35b4a2c553 Fixed gcc warnings and added error handling to shell escape 2013-03-15 10:29:25 +01:00
Clifford Wolf cd5767d61b Added scc pass (find logic loops) 2013-03-15 10:24:08 +01:00
Clifford Wolf 13b2279b6c Added vi .*.swp files to .gitignore 2013-03-15 10:23:53 +01:00
Clifford Wolf 10956cb84a Added [[CITE]] tags to abc and fsm_extract passes 2013-03-15 10:23:02 +01:00
Clifford Wolf 89f009d171 Added additional functionality and cleanups in sigtools.h and celltypes.h 2013-03-15 10:22:23 +01:00
Clifford Wolf 3377a04bf2 Changed prefix for selection operators from # to % 2013-03-14 16:15:24 +01:00
Clifford Wolf 697cf1eb80 Added #ci and #co selection operators 2013-03-14 15:57:47 +01:00
Clifford Wolf b35add5f8c Added more features to #x selection operator 2013-03-14 15:35:05 +01:00
Clifford Wolf b0f386751c Added "select -write" command 2013-03-14 13:02:10 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf de823ce964 Added $sr cell type to celltypes.h 2013-03-14 01:08:30 +01:00
Clifford Wolf 55f927eecb Fixed detection of public wires in opt_rmunused 2013-03-10 14:20:03 +01:00
Clifford Wolf eadf73c823 Added shell escape to command language 2013-03-10 14:05:42 +01:00
Clifford Wolf 0be19f6ca7 Fixed and improved #x selection operator 2013-03-08 10:15:15 +01:00
Clifford Wolf b96ffed69b Automatically select new objects in abc and techmap passes 2013-03-08 09:16:25 +01:00
Clifford Wolf 79b3afa011 Added ## selection operator (union all on stack) 2013-03-08 08:47:35 +01:00
Clifford Wolf 653f0049a8 Added select -count mode 2013-03-08 08:31:12 +01:00
Clifford Wolf ef4f1c55b6 Split extract -attr into extract -cell_attr and -wire_attr 2013-03-08 08:19:24 +01:00
Clifford Wolf bf3a3b9589 Added support for attribute matching in extract pass 2013-03-07 18:51:17 +01:00
Clifford Wolf ed1ddea83b Added portmapping support to subcircuit userCompareNodes() api 2013-03-07 17:54:18 +01:00
Clifford Wolf b070b82187 Cleanups and improvements in Makefile 2013-03-07 17:34:40 +01:00
Clifford Wolf 8960bba9b5 Fixed parsing of select #x<num> operator 2013-03-06 19:01:08 +01:00
Clifford Wolf f2f3e2cb19 Improved error message on failed module load 2013-03-06 18:30:45 +01:00
Clifford Wolf b380af9d6d Added support for loadable modules (aka plugins) 2013-03-06 11:58:07 +01:00
Clifford Wolf 14c097b633 Reset Makefile default config setting (oops) 2013-03-06 09:46:21 +01:00
Clifford Wolf 9f2c7d0936 Fixed mine test case for subcircuit library 2013-03-06 09:44:29 +01:00
Clifford Wolf 594dbc4c93 Fixed handling of constant values and port swapping in subcircuit library 2013-03-06 09:38:47 +01:00
Clifford Wolf 4347423ca6 Changed default value for extract -mine_cells_span 2013-03-05 21:52:57 +01:00
Clifford Wolf 21696c8367 Added some simple progress information to verbose subcircuit miner output 2013-03-05 19:22:59 +01:00
Clifford Wolf 29c17fddf5 Implemented -mine_split option to extract pass 2013-03-05 13:50:31 +01:00
Clifford Wolf 334fd03e1c Implemented much better #x select operator 2013-03-05 12:53:40 +01:00
Clifford Wolf efbb89de1a Implemented extract -mine_max_fanout <num> option 2013-03-03 23:48:00 +01:00
Clifford Wolf f9a5fbf283 Performance optimization in subcircuit mining 2013-03-03 23:17:58 +01:00
Clifford Wolf 441e5fbfca Fixed a gcc compiler warning [-Wparentheses] 2013-03-03 22:45:06 +01:00
Clifford Wolf bc8d94b4ae Added "shared nodes" feature to the subcircuit library 2013-03-03 21:19:55 +01:00
Clifford Wolf 3ebc365c09 Added support for "extract_order" attribute to extract pass 2013-03-03 21:10:27 +01:00
Clifford Wolf d4680fd5a0 Added design->select() api and use it in extract pass 2013-03-03 20:53:24 +01:00