mirror of https://github.com/YosysHQ/yosys.git
corrected typos
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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README
33
README
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@ -29,36 +29,37 @@ synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys c++
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codebase.
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adding additional passes as needed by extending the yosys C++
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code base.
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Yosys is free software licensed under the ISC license (a GPL
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compatible licence that is similar in terms to the MIT license
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compatible license that is similar in terms to the MIT license
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or the 2-clause BSD license).
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Getting Started
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===============
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To build Yosys simply typoe 'make' in this directory. You need
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To build Yosys simply type 'make' in this directory. You need
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a C++ compiler with C++11 support (up-to-date CLANG or GCC is
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recommended) and some standard tools such as GNU Flex, GNU Bison,
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and GNU Make. It might be neccessary to make some changes to
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the config section of the Makefile.
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and GNU Make. It might be necessary to make some changes to
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the config section of the Makefile. The extensive tests require
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Icarus Verilog.
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$ vi Makefile
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$ make
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$ make test
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$ sudo make install
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Yosys can be used using the interactive command shell, using
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synthesis scripts or using command line arguments. Let's perform
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Yosys can be used with the interactive command shell, with
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synthesis scripts or with command line arguments. Let's perform
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a simple synthesis job using the interactive command shell:
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$ ./yosys
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yosys>
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the command "help" can be used to pritn a list of all available
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the command "help" can be used to print a list of all available
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commands and "help <command>" to print details on the specified command:
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yosys> help help
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@ -71,7 +72,7 @@ writing the design to the console in yosys's internal format:
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yosys> write_ilang
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convert processes (always blocks) to netlist elements and perform
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convert processes ("always" blocks) to netlist elements and perform
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some simple optimizations:
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yosys> proc; opt
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@ -178,7 +179,7 @@ Verilog Attributes and non-standard features
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is strongly recommended instead).
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- The "nomem2reg" attribute on modules or arrays prohibits the
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automatic early conversion of arrays to seperate registers.
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automatic early conversion of arrays to separate registers.
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- The "nolatches" attribute on modules or always-blocks
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prohibits the generation of logic-loops for latches. Instead
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@ -188,7 +189,7 @@ Verilog Attributes and non-standard features
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the non-standard {* ... *} attribute syntax to set default attributes
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for everything that comes after the {* ... *} statement. (Reset
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by adding an empty {* *} statement.) The preprocessor define
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__YOSYS_ENABLE_DEFATTR__ must be set in order for this featre to be active.
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__YOSYS_ENABLE_DEFATTR__ must be set in order for this feature to be active.
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TODOs / Open Bugs
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@ -196,7 +197,7 @@ TODOs / Open Bugs
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- Write "design and implementation of.." document
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- Add brief sourcecode documentation to:
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- Add brief source code documentation to:
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- Most passes and kernel functionalities
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@ -206,10 +207,10 @@ TODOs / Open Bugs
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- Constant functions
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- Indexed part selects
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- Multi-dimensional arrays
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- ROM modelling using "initial" blocks
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- ROM modeling using "initial" blocks
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- The "defparam <cell_name>.<parameter_name> = <value>;" syntax
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- Builtin primitive gates (and, nand, cmos, nmos, pmos, etc..)
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- Ignore what needs to be ignored (e.g. drive and charge strenghts)
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- Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..)
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- Ignore what needs to be ignored (e.g. drive and charge strengths)
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- Check standard vs. implementation to identify missing features
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- Actually use range information on parameters
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