mirror of https://github.com/YosysHQ/yosys.git
Added some simple progress information to verbose subcircuit miner output
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@ -1316,6 +1316,7 @@ class SubCircuit::SolverWorker
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if (verbose)
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my_printf("\nMining for frequent subcircuits of size %d using increment %d:\n", oldSetSize+increment, increment);
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int count = 0;
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for (auto &it : poolPerGraph)
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{
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std::map<int, std::set<int>> node2sets;
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@ -1326,7 +1327,7 @@ class SubCircuit::SolverWorker
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node2sets[node].insert(idx);
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}
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for (int idx1 = 0; idx1 < int(it.second.size()); idx1++)
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for (int idx1 = 0; idx1 < int(it.second.size()); idx1++, count++)
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{
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std::set<int> idx2set;
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@ -1350,7 +1351,7 @@ class SubCircuit::SolverWorker
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const auto &graph = graphData[it.first].graph;
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if (verbose) {
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my_printf("Set %s[", graphId.c_str());
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my_printf("<%d%%/%d> Found %s[", int(100*count/pool.size()), oldSetSize+increment, graphId.c_str());
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bool first = true;
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for (int nodeIdx : mergedSet.nodes) {
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my_printf("%s%s", first ? "" : ",", graph.nodes[nodeIdx].nodeId.c_str());
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