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2582 Commits

Author SHA1 Message Date
Eddie Hung 1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut 
Interpret "abc9 -lut" as lut string only if [0-9:]
 2019-12-20 13:09:00 -08:00
Eddie Hung 269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565 
Fix sim for assignments with lhs<rhs size
 2019-12-19 12:24:27 -05:00
Eddie Hung 3b559de6e9 Interpret "abc9 -lut" as lut string only if [0-9:] 2019-12-18 12:21:12 -08:00
Eddie Hung d0afe4e10d Merge branch 'master' of github.com:YosysHQ/yosys 2019-12-18 12:08:38 -08:00
Eddie Hung b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
N. Engelhardt 3671ecc7d0 use extra_args 2019-12-18 12:30:30 +01:00
Clifford Wolf 41ed6ca7a5 Fix sim for assignments with lhs<rhs size, fixes #1565 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-17 17:36:30 +01:00
Eddie Hung dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung 33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung 187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung 4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung 6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung 503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Eddie Hung 952d62991f Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr 2019-12-16 12:07:49 -08:00
Diego H 87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
N. Engelhardt abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Alyssa Milburn e709fd3da1 Fix opt_expr.eqneq.cmpzero debug print 2019-12-15 20:40:38 +01:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
N. Engelhardt ce3615b367 add periods and newlines to help message 2019-12-13 10:28:34 +01:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
N. Engelhardt 4c7cda1c8b add a command to read/modify scratchpad contents 2019-12-12 16:25:03 +01:00
Eddie Hung 7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung 36a88be609 ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
Eddie Hung bbdf2452b3 -unwrap to create $lut not SB_LUT4 for opt_lut 2019-12-09 13:27:09 -08:00
Eddie Hung 500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Eddie Hung 946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Eddie Hung a7e0cca480 Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:18 -08:00
Marcin Kościelnicki 2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung 5897b918b3 ice40_wrapcarry to preserve SB_CARRY's attributes 2019-12-03 14:48:11 -08:00
David Shah e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Eddie Hung 6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd 
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
 2019-11-27 08:00:22 -08:00
Clifford Wolf 41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr 
memory_collect: Copy attr from RTLIL::Memory to  cell
 2019-11-27 11:25:23 +01:00
Marcin Kościelnicki fdcbda195b opt_share: Fix handling of fine cells. 
Fixes #1525.
 2019-11-27 08:01:07 +01:00
Eddie Hung 2105ae176a Check for either sign or zero extension for postAdd packing 2019-11-26 22:51:00 -08:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Clifford Wolf 03fb92ed6f Add "opt_mem" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 17:45:22 +01:00
David Shah ca99b1ee8d proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 20:46:41 +00:00
Marcin Kościelnicki 15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
David Shah 7ff5d6d30a memory_collect: Copy attr from RTLIL::Memory to cell 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 13:58:03 +00:00
Marcin Kościelnicki 38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
Clifford Wolf 527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst 
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
 2019-11-17 10:42:30 +01:00
David Shah f5804a84fd wreduce: Don't trim zeros or sext when not matching ARST_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-14 18:43:15 +00:00
Clifford Wolf e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf 07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
whitequark ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes 
flowmap: fix a few crashes
 2019-11-13 11:57:17 +00:00
Clifford Wolf 4be5a0fd7c Update fsm_detect bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 17:31:30 +01:00
Clifford Wolf 16df8f5a32 Bugfix in fsm_detect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 14:26:02 +01:00