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yosys
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1,445 Commits 87 Branches 48 Tags 34 MiB
Commit Graph

37 Commits

Author SHA1 Message Date
Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00
Clifford Wolf b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax 2014-08-04 15:40:07 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf ee8ad72fd9 fixed parsing of constant with comment between size and value 2014-07-02 06:27:04 +02:00
Clifford Wolf 0c4c79c4c6 Fixed parsing of TOK_INTEGER (implies TOK_SIGNED) 2014-06-16 15:02:40 +02:00
Clifford Wolf 9bd7d5c468 Added handling of real-valued parameters/localparams 2014-06-14 12:00:47 +02:00
Clifford Wolf 7ef0da32cd Added Verilog lexer and parser support for real values 2014-06-13 11:29:23 +02:00
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 5281562d0e made the generate..endgenrate keywords optional 2014-06-06 23:05:01 +02:00
Clifford Wolf b5cd7a0179 added while and repeat support to verilog parser 2014-06-06 17:40:04 +02:00
Clifford Wolf a1be4816d6 Replaced depricated %name-prefix= bison directive 2014-04-20 14:22:11 +02:00
Clifford Wolf 02e6f2c5be Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
Clifford Wolf 007bdff55d Added support for functions returning integer 2014-02-12 23:29:54 +01:00
Clifford Wolf d06258f74f Added constant size expression support of sized constants 2014-02-01 13:50:23 +01:00
Clifford Wolf 9a1eb45c75 Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
Clifford Wolf ecc30255ba Added proper === and !== support in constant expressions 2013-12-27 13:50:08 +01:00
Clifford Wolf 5c39948ead Added AstNode::mkconst_str API 2013-12-05 12:53:49 +01:00
Clifford Wolf 4a4a3fc337 Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
Clifford Wolf 507c63d112 Added support for local regs in named blocks 2013-12-04 09:10:16 +01:00
Clifford Wolf 1de12e1efc Improved handling of initialized registers 2013-11-23 16:26:59 +01:00
Clifford Wolf 92035fb38e Implemented indexed part selects 2013-11-20 13:05:27 +01:00
Clifford Wolf 19dba2561e Implemented part/bit select on memory read 2013-11-20 10:51:32 +01:00
Clifford Wolf e340532ce5 Added init= attribute for fpga-style reset values 2013-11-20 01:49:37 +01:00
Clifford Wolf 0dfdbd991a Fixed parsing of module arguments when one type is used for many args 2013-11-19 20:35:31 +01:00
Clifford Wolf 63060dcd2e Fixed parsing of "parameter integer" 2013-11-13 15:30:23 +01:00
Clifford Wolf f050c40519 Various fixes for correct parameter support 2013-11-07 10:02:11 +01:00
Clifford Wolf 23cf23418c Fixed handling of boolean attributes (frontends) 2013-10-24 11:20:13 +02:00
Clifford Wolf eae43e2db4 Fixed handling of boolean attributes (kernel) 2013-10-24 10:59:27 +02:00
Clifford Wolf 56432a920f Added defparam support to Verilog/AST frontend 2013-07-04 14:12:33 +02:00
Clifford Wolf 0c6ffc4c65 More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
Clifford Wolf 46fbe9d262 Added SAT generator and simple sat_solve command 2013-06-07 13:59:13 +02:00
Clifford Wolf 161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
Clifford Wolf e45d1c8865 Tiny fixes to verilog parser 2013-03-23 18:54:31 +01:00
Clifford Wolf 4f0c2862a0 Added support for verilog genblock[index].member syntax 2013-02-26 13:18:22 +01:00
Clifford Wolf 6d1502b948 Added support for "always @(*)" 2013-01-16 17:32:11 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00