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1,136 Commits 90 Branches 51 Tags 36 MiB
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209 Commits

Author SHA1 Message Date
Clifford Wolf 48dc6ab98d Improved AstNode::asReal for large integers 2014-06-15 08:38:31 +02:00
Clifford Wolf 149fe83a8d improved (fixed) conversion of real values to bit vectors 2014-06-14 21:00:51 +02:00
Clifford Wolf d5765b5e14 Fixed relational operators for const real expressions 2014-06-14 19:33:58 +02:00
Clifford Wolf f3b4a9dd24 Added support for math functions 2014-06-14 13:36:23 +02:00
Clifford Wolf 9bd7d5c468 Added handling of real-valued parameters/localparams 2014-06-14 12:00:47 +02:00
Clifford Wolf fc7b6d172a Implemented more real arithmetic 2014-06-14 11:27:05 +02:00
Clifford Wolf 442a8e2875 Implemented basic real arithmetic 2014-06-14 08:51:22 +02:00
Clifford Wolf 9dd16fa41c Added real->int convertion in ast genrtlil 2014-06-14 07:44:19 +02:00
Clifford Wolf 7ef0da32cd Added Verilog lexer and parser support for real values 2014-06-13 11:29:23 +02:00
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 0b1ce63a19 Added support for repeat stmt in const functions 2014-06-07 10:47:53 +02:00
Clifford Wolf 7c8a7b2131 further improved const function support 2014-06-07 00:02:05 +02:00
Clifford Wolf 5281562d0e made the generate..endgenrate keywords optional 2014-06-06 23:05:01 +02:00
Clifford Wolf 76da2fe172 improved const function support 2014-06-06 22:55:02 +02:00
Clifford Wolf 5c10d2ee36 fix functions with no block (but single statement, loop, etc.) 2014-06-06 21:29:23 +02:00
Clifford Wolf ab54ce17c8 improved ast simplify of const functions 2014-06-06 17:40:45 +02:00
Clifford Wolf b5cd7a0179 added while and repeat support to verilog parser 2014-06-06 17:40:04 +02:00
Clifford Wolf f9c1cd5edb Improved error message for options after front-end filename arguments 2014-06-04 09:10:50 +02:00
Johann Glaser 63dfbb18cf new flags -ignore_miss_func and -ignore_miss_dir for read_liberty 2014-05-28 16:50:13 +02:00
Clifford Wolf 7188542155 Fixed clang -Wdeprecated-register warnings 2014-04-20 14:28:23 +02:00
Clifford Wolf a1be4816d6 Replaced depricated %name-prefix= bison directive 2014-04-20 14:22:11 +02:00
Clifford Wolf a3b9692a68 Fixed mapping of Verific WIDE_DFFRS operator 2014-03-20 13:40:01 +01:00
Clifford Wolf 470c2455e4 Fixed mapping of Verific FADD primitive with unconnected outputs 2014-03-20 13:26:52 +01:00
Clifford Wolf cdf1257565 Progress in Verific bindings 2014-03-17 14:43:16 +01:00
Clifford Wolf 0b0dcfda7d Progress in Verific bindings 2014-03-17 02:43:53 +01:00
Clifford Wolf a67cd2d4a2 Progress in Verific bindings 2014-03-17 01:56:00 +01:00
Clifford Wolf acda74c12c Added support for memories to verific bindings 2014-03-16 17:05:05 +01:00
Clifford Wolf 7545510edc Use Verific Net::{IsGnd,IsPwr} API in Verific bindings 2014-03-16 16:06:03 +01:00
Clifford Wolf 0ebee4c8e7 Progress in Verific bindings 2014-03-15 22:51:12 +01:00
Clifford Wolf fc2c821407 Progress in Verific bindings 2014-03-15 15:31:54 +01:00
Clifford Wolf 1d00ad9d4d Progress in Verific bindings 2014-03-15 14:36:11 +01:00
Clifford Wolf e37d672ae7 Progress in Verific bindings 2014-03-14 16:40:25 +01:00
Clifford Wolf 0ac915a757 Progress in Verific bindings 2014-03-14 11:46:13 +01:00
Clifford Wolf 9a1accf692 Progress in Verific bindings 2014-03-13 18:21:00 +01:00
Clifford Wolf 6a53bc7b27 Copy Verific vdbs files to Yosys "share" data directory 2014-03-13 17:34:31 +01:00
Clifford Wolf 7a1ac11203 Added test_navre.ys for verific frontend 2014-03-13 13:12:06 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf 9992026a8d Added support for `line compiler directive 2014-03-11 14:06:57 +01:00
Clifford Wolf 5a15539c9b Improved verific command (added support for some operators) 2014-03-10 12:06:57 +01:00
Clifford Wolf c71791a1ff Improvements in verific command 2014-03-10 03:03:08 +01:00
Clifford Wolf 8d06f9f2fe Added "verific" command 2014-03-09 20:40:04 +01:00
Clifford Wolf 620d51d9f7 Bugfix in ilang frontend autoidx recovery 2014-03-07 17:19:14 +01:00
Clifford Wolf 4d07f88258 Fixed gcc compiler warning 2014-03-06 16:37:19 +01:00
Clifford Wolf 09805ee9ec Include id2ast pointers when dumping AST 2014-03-05 19:56:31 +01:00
Clifford Wolf d6a01fe412 Fixed merging of compatible wire decls in AST frontend 2014-03-05 19:55:58 +01:00
Clifford Wolf de7bd12004 Bugfix in recursive AST simplification 2014-03-05 19:45:33 +01:00
Clifford Wolf ef90236a5d Fixed vhdl2verilog temp dir name 2014-03-01 17:48:15 +01:00
Clifford Wolf 04999f4af0 Fixed vhdl2verilog help message 2014-03-01 17:47:19 +01:00