riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,208 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

6208 Commits

Author SHA1 Message Date
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf 8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Clifford Wolf 6d64e242ba Fix handling of "logic" variables with initial value 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:25:11 +02:00
Clifford Wolf b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
Clifford Wolf eb3b9fb24a
Merge pull request #1104 from whitequark/case-semantics 
Clarify switch/case semantics in RTLIL
 2019-06-19 10:50:32 +02:00
whitequark addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
whitequark df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky 4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00
Ben Widawsky 468c41d997 Support ~ for home directory 
This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:38:40 -07:00
Eddie Hung 7324a4c2cd Remove iterator based Module::remove as per @cliffordwolf 2019-06-18 12:47:12 -07:00
Eddie Hung 6a4025b5ee Remove unncessary header 2019-06-18 12:37:46 -07:00
Eddie Hung ad9658ea5b Merge remote-tracking branch 'origin/master' into xaig 2019-06-18 12:32:42 -07:00
Eddie Hung e5aa3feb1b Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-18 12:19:22 -07:00
Eddie Hung 776d7cea6a Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-18 11:51:34 -07:00
Eddie Hung 4ca847a217 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-18 11:49:54 -07:00
Eddie Hung 8e0a47fb92 Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Eddie Hung 8f5e6d73ff Revert "Fix (do not) permute LUT inputs, but permute mux selects" 
This reverts commit da3d2eedd2.
 2019-06-18 11:35:21 -07:00
Eddie Hung 3d283e69f8 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-18 09:51:28 -07:00
Eddie Hung b304744d15 Clean up 2019-06-18 09:50:37 -07:00
Eddie Hung da3d2eedd2 Fix (do not) permute LUT inputs, but permute mux selects 2019-06-18 09:49:57 -07:00
Clifford Wolf 64947453e2
Merge pull request #1086 from udif/pr_elab_sys_tasks2 
Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
 2019-06-18 16:52:08 +02:00
Eddie Hung 2b0e28b261 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 22:29:34 -07:00
Eddie Hung 608a95eb01 Fix copy-pasta issue 2019-06-17 22:29:22 -07:00
Eddie Hung 59b4e69d16 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 22:25:14 -07:00
Eddie Hung 2a35c4ef94 Permute INIT for +/xilinx/lut_map.v 2019-06-17 22:24:35 -07:00
Eddie Hung 75f8b4cf10 Simplify comment 2019-06-17 19:14:41 -07:00
Eddie Hung 9d56c0d525 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 18:25:35 -07:00
Eddie Hung 840562943f Update LUT7/8 delays to take account for [ABC]OUTMUX delay 2019-06-17 17:06:01 -07:00
Eddie Hung 8d40830ee4 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 13:33:47 -07:00
Eddie Hung 4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung 4b9eefe3b6 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 13:20:29 -07:00
Eddie Hung 63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung 0c9cf89239 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 12:59:05 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung 76a72283e2 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 10:38:54 -07:00
Eddie Hung c15ee827f4 Try -W 300 2019-06-17 10:29:06 -07:00
Eddie Hung 7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Clifford Wolf c23bbc4291 Add timescale and generated-by header to yosys-smtbmc MkVcd 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-16 23:12:03 +02:00
Eddie Hung 1ec450d6bf Try -W 300 2019-06-16 12:08:03 -07:00
Eddie Hung 5f9ba3ea41 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-16 12:05:07 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 842c110357 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-15 05:48:47 -07:00
Eddie Hung bf312043d4 Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O 2019-06-15 05:45:16 -07:00
Eddie Hung 627ea0b2a9 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-14 14:20:36 -07:00
Eddie Hung 7ff8330d1e Leave breadcrumb behind 2019-06-14 13:34:40 -07:00
Eddie Hung 46e69ee934 Remove redundant condition 2019-06-14 13:31:18 -07:00
Eddie Hung 9b55e69755 Revert "Cleanup/optimise toposort in write_xaiger" 
This reverts commit 1948e7c846.

Restores old toposort with optimisations
 2019-06-14 13:29:36 -07:00
Eddie Hung 4d7516f459 Revert "Cleanup/optimise toposort in write_xaiger" 
This reverts commit 1948e7c846.

Restores old toposort with optimisations
 2019-06-14 13:28:47 -07:00
Eddie Hung 6c5ed8b660 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-14 13:15:12 -07:00
Eddie Hung 746f70a9ce Update comment 2019-06-14 13:10:46 -07:00