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9063 Commits

Author SHA1 Message Date
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Claire Wolf 3477749459 Bump YOSYS_VER 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-02 15:40:00 +02:00
Claire Wolf d1fc4321f0
Merge pull request #1770 from YosysHQ/claire/btor_symbols 
Improve write_btor symbol handling
 2020-04-02 15:38:47 +02:00
Claire Wolf 104c004e6d
Merge pull request #1765 from YosysHQ/claire/btor_info 
Add info-file and cover features to write_btor
 2020-04-02 15:38:27 +02:00
Claire Wolf 8b7610c48b
Merge pull request #1777 from YosysHQ/claire/manyhot 
Using LFSR counter for ezSAT::manyhot()
 2020-04-02 14:31:33 +02:00
Claire Wolf 65a3ff69bd Improve ezsat onehot encoding scheme 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-02 12:22:28 +02:00
Claire Wolf f72b65b2a5 Using LFSR counter for ezSAT::manyhot() 
The only user of this API right now is the puzzle3d benchmark and
it sees a slight reduction in CNF size from this, but the performance
difference is within the noise of measurement on my system.

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-02 11:37:12 +02:00
Eddie Hung c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup 
kernel: share a single CellTypes within a pass
 2020-04-01 14:17:45 -07:00
Eddie Hung 4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 
opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
 2020-04-01 14:17:01 -07:00
Eddie Hung e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu 
opt_expr: improve performance on $alu and $sub
 2020-04-01 14:11:09 -07:00
David Shah f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc 
verilog: Add location info for generate constructs
 2020-04-01 20:55:24 +01:00
Eddie Hung d8dd842c09
Merge pull request #1852 from boqwxp/cleanup_synth_ice40 
Fix indentation in `techlibs/ice40/synth_ice40.cc`.
 2020-04-01 11:18:38 -07:00
David Shah c3997c77a5 verilog: Add location info for generate constructs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-01 18:47:20 +01:00
Eddie Hung 86380e0212
Merge pull request #1849 from boqwxp/cleanup_kernel_yosys 
Clean up pseudo-private member usage in `kernel/yosys.cc`.
 2020-04-01 09:35:35 -07:00
Eddie Hung 903cec84f4
Merge pull request #1850 from boqwxp/cleanup_backends 
Cleanup pseudo-private member usage and outdated `RTLIL::id2cstr()` in backends
 2020-04-01 09:34:02 -07:00
Alberto Gonzalez fc6b898178
Fix indentation in `techlibs/ice40/synth_ice40.cc`. 2020-04-01 16:29:56 +00:00
Alberto Gonzalez c23c2c59c1
Update `RTLIL::id2cstr()` usage to `log_id`. 2020-04-01 06:53:28 +00:00
Claire Wolf 926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice 
ast: simplify to fully populate dynamic slicing case transformation
 2020-04-01 08:38:14 +02:00
Alberto Gonzalez cdb14652be
Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`. 2020-04-01 06:32:09 +00:00
Alberto Gonzalez 24ef73904f
Clean up pseudo-private member usage in `backends/blif/blif.cc`. 2020-04-01 05:50:48 +00:00
Alberto Gonzalez f657fed24c
Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`. 2020-04-01 05:25:10 +00:00
Alberto Gonzalez 68c0e3562e
Clean up pseudo-private member usage in `backends/spice/spice.cc`. 2020-04-01 04:56:52 +00:00
Alberto Gonzalez 057976c323
Clean up pseudo-private member usage in `backends/edif/edif.cc`. 2020-04-01 04:37:07 +00:00
Alberto Gonzalez 68fef4ca7f
Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`. 2020-04-01 03:08:39 +00:00
Alberto Gonzalez ae05795f54
Clean up pseudo-private member usage in `kernel/yosys.cc`. 2020-04-01 02:53:56 +00:00
Eddie Hung 1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup 
opt_merge: speedup
 2020-03-31 14:50:32 -07:00
Eddie Hung 5132f4099b ast: simplify to fully populate dynamic slicing case transformation 2020-03-31 11:52:14 -07:00
Eddie Hung 3df66027e0 Add dynamic slicing Verilog testcase 2020-03-31 11:51:31 -07:00
Eddie Hung 05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Eddie Hung 3e88ede061
Merge pull request #1835 from boqwxp/cleanup_sat_expose 
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
 2020-03-30 13:05:12 -07:00
Eddie Hung 0d878ca256
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design 
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
 2020-03-30 11:56:17 -07:00
Eddie Hung 2c0739cbad
Merge pull request #1786 from boqwxp/hierarchycc_cleanup 
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
 2020-03-30 11:37:51 -07:00
Alberto Gonzalez b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
Eddie Hung 9f7d20a653
Merge pull request #1831 from boqwxp/cleanup_sat_eval 
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
 2020-03-30 11:13:53 -07:00
Eddie Hung 769c7318e7
Merge pull request #1833 from boqwxp/cleanup_sat_freduce 
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
 2020-03-30 11:13:06 -07:00
Alberto Gonzalez 00544cffab
Remove unused function parameter. 2020-03-30 18:00:19 +00:00
Alberto Gonzalez 5a0f029e23
Simplify iterating over selected modules or cells. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-03-30 17:56:07 +00:00
Alberto Gonzalez 7fc0938bb6
Replace `RTLIL::id2cstr()` with `log_id()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:50:36 +00:00
Alberto Gonzalez 4c92f9380c
Fix double deletion in `passes/hierarchy/hierarchy.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:43:54 +00:00
Alberto Gonzalez f4faa1514b
Further clean up `passes/sat/eval.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:38:35 +00:00
Alberto Gonzalez 9f265dfd3f
Further clean up `passes/sat/freduce.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:25:30 +00:00
Alberto Gonzalez 696660351f
Clean up more in `passes/sat/expose.cc`. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-03-30 16:16:16 +00:00
Eddie Hung 1d93d1e59f memory_share: fix stray brace 2020-03-30 08:35:40 -07:00
Eddie Hung 4d897975a8 Code review fixes 2020-03-30 08:22:46 -07:00
Eddie Hung f64d59d824
Apply suggestions from code review 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-03-30 08:19:56 -07:00
N. Engelhardt d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
N. Engelhardt 2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines 
Add support for SystemVerilog-style `define to Verilog frontend
 2020-03-30 13:51:12 +02:00
Miodrag Milanovic 1dbc701728 Explicit include of csignal 2020-03-28 09:49:08 +01:00
Miodrag Milanovic 5cdcd6ec79 windows - there are no stopping signals 2020-03-28 09:09:11 +01:00
Alberto Gonzalez 1197a43380
Clean up pseudo-private member usage in `passes/sat/expose.cc`. 2020-03-28 06:18:09 +00:00