Clifford Wolf
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4440610d3f
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Added liberty frontend
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2014-02-15 12:57:28 +01:00 |
Clifford Wolf
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45d2b6ffce
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Be more conservative with new const-function code
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2014-02-14 20:45:30 +01:00 |
Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
Clifford Wolf
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3121d19d95
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Added abc -keepff option
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2014-02-14 11:28:42 +01:00 |
Clifford Wolf
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de3ea9269a
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updated default ABC command strings
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2014-02-13 19:14:15 +01:00 |
Clifford Wolf
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a123941618
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Updated ABC
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2014-02-13 18:56:36 +01:00 |
Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
Clifford Wolf
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b463907890
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Removed double blanks in ABC default command sequences
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2014-02-13 08:12:52 +01:00 |
Clifford Wolf
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c6236c9e97
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-13 08:09:17 +01:00 |
Clifford Wolf
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7664f5d92b
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Updated ABC and some related changes
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2014-02-13 08:07:08 +01:00 |
Clifford Wolf
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6b210d2b6f
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Merge pull request #26 from ahmedirfan1983/btor
Btor
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2014-02-12 23:46:58 +01:00 |
Clifford Wolf
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08caa631dd
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-12 23:30:02 +01:00 |
Clifford Wolf
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007bdff55d
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Added support for functions returning integer
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2014-02-12 23:29:54 +01:00 |
Ahmed Irfan
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ac896c63e2
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modified btor synthesis script for correct use of splice command.
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2014-02-12 13:38:28 +01:00 |
Clifford Wolf
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9ce7b0fc3b
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Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)
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2014-02-12 13:11:58 +01:00 |
Clifford Wolf
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ab71bd0746
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Updated ABC to rev e97a6e1d59b9
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2014-02-12 08:35:42 +01:00 |
Clifford Wolf
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0defc86519
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renamed ilang "scope error" to "ilang error"
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2014-02-11 19:17:07 +01:00 |
Ahmed Irfan
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45e468114a
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disabling splice command in the script
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2014-02-11 15:43:03 +01:00 |
Ahmed Irfan
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1d64b3e008
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register output corrected
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2014-02-11 13:28:05 +01:00 |
Ahmed Irfan
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1a2dc48c2a
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
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2014-02-11 13:26:43 +01:00 |
Ahmed Irfan
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e8f6b8f201
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added concat and slice cell translation
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2014-02-11 13:06:01 +01:00 |
Clifford Wolf
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d2fd45949d
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More Makefile cleanups
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2014-02-11 12:58:08 +01:00 |
Clifford Wolf
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4bd2d47e45
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Improved "make manual" and "make clean"
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2014-02-11 12:55:58 +01:00 |
Clifford Wolf
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fb186e6299
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Improved ilang parser error messages
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2014-02-09 15:35:31 +01:00 |
Clifford Wolf
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d229324420
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fixed a bug in subcircuit library with cells that have connections to itself
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2014-02-09 15:27:58 +01:00 |
Clifford Wolf
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38469e7686
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Various improvements in expose command (added -sep and -cut)
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2014-02-09 11:07:46 +01:00 |
Clifford Wolf
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b6f33576d5
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Added delete {-input|-output|-port}
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2014-02-09 10:03:26 +01:00 |
Clifford Wolf
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b3b5fac191
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Bugfix in delete command
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2014-02-09 09:34:58 +01:00 |
Clifford Wolf
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039bb456cc
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Added test cases for expose -evert-dff
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2014-02-08 21:31:56 +01:00 |
Clifford Wolf
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85914c36e5
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Fixed handling of async reset in expose -evert-dff
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2014-02-08 21:26:40 +01:00 |
Clifford Wolf
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db86aaa07d
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Build fixes for log cmd
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2014-02-08 21:21:51 +01:00 |
Clifford Wolf
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c06de50f05
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-08 21:08:46 +01:00 |
Clifford Wolf
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0935e20003
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Implemented expose -evert-dff
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2014-02-08 21:08:38 +01:00 |
Clifford Wolf
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793290a304
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Merge pull request #24 from hansiglaser/master
added "log" command
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2014-02-08 20:02:32 +01:00 |
Johann Glaser
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af14bb5f65
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added "log" command
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2014-02-08 19:19:32 +01:00 |
Clifford Wolf
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8f9c707a4c
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Improved checking of internal cell conventions
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2014-02-08 19:13:49 +01:00 |
Clifford Wolf
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7f52c18a22
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Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
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2014-02-08 19:13:19 +01:00 |
Clifford Wolf
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926fa61119
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Added various new options to splice command
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2014-02-08 16:37:18 +01:00 |
Clifford Wolf
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0c11d04144
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Added %a select operator
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2014-02-08 16:31:38 +01:00 |
Clifford Wolf
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6644f80d97
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Moved some passes to other source directories
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2014-02-08 14:39:15 +01:00 |
Clifford Wolf
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03ee63ff80
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Added support for "keep" attribute to abc pass
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2014-02-08 14:25:29 +01:00 |
Clifford Wolf
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82c98bbbe6
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Added opt -purge (frontend to opt_clean -purge)
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2014-02-08 14:21:34 +01:00 |
Clifford Wolf
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922d1c9520
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Only count non-trivial attributes when findinf master signal in opt_clean
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2014-02-08 14:21:04 +01:00 |
Clifford Wolf
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669a6e462d
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Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output
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2014-02-08 12:27:38 +01:00 |
Clifford Wolf
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2c51619c2b
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Now also move net labes to the right position in splice cmd
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2014-02-08 00:06:00 +01:00 |
Clifford Wolf
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274bcef66c
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Improved detection of primary wire for a signal in opt_clean
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2014-02-07 23:50:17 +01:00 |
Clifford Wolf
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244e8ce1f4
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Added splice command
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2014-02-07 20:30:56 +01:00 |
Clifford Wolf
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08aa1062b4
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Added log_header() to splitnets
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2014-02-07 19:51:15 +01:00 |
Clifford Wolf
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d85a6bf5d3
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Added $slice and $concat to CellTypes list
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2014-02-07 19:50:44 +01:00 |