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1573 Commits

Author SHA1 Message Date
Emil J. Tywoniak 2489711c39 hashlib: legacy mkhash_add -> djb2_add 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 838eb9c280 hashlib: acc -> eat 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 4c07564203 hashlib: add deprecated mkhash function to prevent plugin breakage 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 9ff80b3cd5 docs: document the ideas behind the hashing interface 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 82874fd631 hashlib: run_hash uses hash_top_ops, not hash_ops 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 60c1e41557 hashlib: remove is_new from HasherDJB32, implement hash_top for IdString 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 8513021e0b hashlib: restore hash_obj_ops for pointers to indexed types 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 681736ddeb hash: solo hashing interface, override for SigBit 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak dc7070b71f hashlib: prevent naive hashing of IdString when hashing SigBit 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 4d6b709d70 hashlib: allow forcing Hasher state, use it for IdString trivial hashing 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak e21932c4e0 hashlib: don't xorshift in between upper and lower word 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 0ba66f3bfe hashlib: fudge always 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 148583dcaf hashlib: hash_t can be set to 64-bit 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 0758142b88 hashlib: use hash_t across the board 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak e626fafa5e hashlib: only include in one place 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak c26f625b27 hashlib: fix pyosys 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 3bd50682d8 driver: add --hash-seed 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 898d042604 hashlib: redo interface for flexibility 2024-11-26 10:52:07 +01:00
Martin Povišer 270846a49a
Merge pull request #4723 from povik/memv2-nordports 
rtlil: Adjust internal check for `$mem_v2` cells
 2024-11-18 15:44:39 +01:00
Martin Povišer 1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions 
read_liberty extensions
 2024-11-18 14:42:18 +01:00
Martin Povišer 2dba345049 portarcs: New command to derive propagation arcs 2024-11-13 16:20:35 +01:00
Martin Povišer 4ce8c7a0d3
Merge pull request #4709 from YosysHQ/emil/idstring-in-fold 
functional, glift: use fold overload of IdString::in instead of pool …
 2024-11-13 15:17:33 +01:00
Martin Povišer c7e8d41600 read_liberty: Set `area` `capacitance` attributes 2024-11-12 13:26:38 +01:00
Robin Ole Heinemann 8bc4bd8a20 cxxrtl, fmt: escape double quotes in c strings 2024-11-11 18:49:05 +00:00
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for `$mem_v2` cells 
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
 2024-11-08 15:18:43 +01:00
N. Engelhardt 2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing 2024-11-06 16:29:07 +01:00
N. Engelhardt 9068ec5566
Merge pull request #4627 from RCoeurjoly/roland/assume_x 2024-11-06 16:27:30 +01:00
Emil J. Tywoniak 387a235158 functional, glift: use fold overload of IdString::in instead of pool literals 2024-11-06 12:48:32 +01:00
Emil J b2d78589e2
Merge pull request #4675 from YosysHQ/emil/pyosys-fix-segfault 
yosys: fix pyosys initialization segfault
 2024-11-01 16:40:58 +01:00
Lofty dd7ea0ab6c qwp: remove 2024-10-25 14:09:58 +01:00
Emil J 7db4c65970
Merge pull request #4672 from YosysHQ/emil/fix-tcl-args-cxxopts 
driver: fix special args passing to tcl and python
 2024-10-21 15:41:24 +02:00
Emil J. Tywoniak 37e61b993a yosys: fix pyosys initialization segfault 2024-10-18 11:56:13 +02:00
Emil J 799497ebba
Merge pull request #4671 from YosysHQ/emil/const-deref-pyosys 
py_wrap: implement nested class definitions
 2024-10-18 11:46:12 +02:00
Emil J. Tywoniak 49d8a35c2e rtlil: appease py_wrap 2024-10-18 11:31:20 +02:00
Emil J. Tywoniak 0341265e64 driver: fix special args passing to tcl and python 2024-10-16 23:56:45 +02:00
Emil J. Tywoniak e9e67f381c rtlil: remove trailing comma as pyosys workaround 2024-10-16 23:15:06 +02:00
Krystine Sherwin 4ea6119734
cmdref: Move html only section inside cmd:def 
Fixes missing links in body and `??` in tag/command index.
Update synth.rst to match.
 2024-10-17 06:06:57 +13:00
Krystine Sherwin b1025dbaa6
cellhelp.py: Cells can have tags 
Tags are added to the list of properties when exporting to `cells.json`.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin 04b0ae540d
cellref: Move default help message to register.cc 
Drop the default help message from rst while still displaying it on the command line.
Fix command line formatting for older style help messages.
 2024-10-15 07:31:47 +13:00
Krystine Sherwin b127ac07f8
Docs: Preliminary autocellgroup usage 
Remove `/source/cell` from .gitignore.
Add a few initial cell pages.
Add YosysCellGroup documenter and cell:group directive.
Update Documenters to use nested json.
Better nested tocs for group.module.source layout.
 2024-10-15 07:26:04 +13:00
Krystine Sherwin 7c5b10fe50
cellref: Add json dump 
New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
 2024-10-15 07:25:27 +13:00
Krystine Sherwin 063a6bc2d7
register.cc: Include properties in docs 2024-10-15 07:23:45 +13:00
Krystine Sherwin 4c9c4c1419
celltypes.h: Add extra properties 2024-10-15 07:23:45 +13:00
Krystine Sherwin 21747c468c
Docs: Improve cell_help usage 
- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
  preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
  reporting errors for any cells defined in `cell_types` but not
  `cell_help_messages`.
 2024-10-15 07:23:45 +13:00
Krystine Sherwin f9b4e04fef
Docs: Add cell reference 
Subclass the command reference code in order to support smart references to the internal cells.
 2024-10-15 07:17:36 +13:00
Krystine Sherwin c98d134662
cellhelp: Extra newline 
Fix `$macc` page.
 2024-10-15 07:17:35 +13:00
Krystine Sherwin d629aa6bf1
cellhelp: Split gate-level and word-level cells 2024-10-15 07:17:35 +13:00
Krystine Sherwin 57cd8d29db
cellhelp: Add default format parse for simcells 
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
 2024-10-15 07:16:40 +13:00
Krystine Sherwin a2b2904ed8
cellhelp: Add source line to help 
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
 2024-10-15 07:16:40 +13:00
Krystine Sherwin 784292626e
cellhelp: Rename short_desc to title 2024-10-15 07:16:39 +13:00