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Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing

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N. Engelhardt 2024-11-06 16:29:07 +01:00 committed by GitHub
parent 9068ec5566 76c615b2ae
commit 2de9f00368
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GPG Key ID: B5690EEEBB952194
5 changed files with 88 additions and 1 deletions
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10
kernel/fstdata.cc
View File

@ -137,14 +137,22 @@ void FstData::extractVarNames()
if (!var.is_alias)
handle_to_var[h->u.var.handle] = var;
std::string clean_name;
bool has_space = false;
for(size_t i=0;i<strlen(h->u.var.name);i++)
{
char c = h->u.var.name[i];
if(c==' ') break;
if(c==' ') { has_space = true; break; }
clean_name += c;
}
if (clean_name[0]=='\\')
clean_name = clean_name.substr(1);
if (!has_space) {
size_t pos = clean_name.find_last_of("[");
std::string index_or_range = clean_name.substr(pos+1);
if (index_or_range.find(":") != std::string::npos) {
clean_name = clean_name.substr(0,pos);
}
}
size_t pos = clean_name.find_last_of("<");
if (pos != std::string::npos && clean_name.back() == '>') {
std::string mem_cell = clean_name.substr(0, pos);

28
tests/sim/var_reference_with_whitespace.vcd Normal file
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@ -0,0 +1,28 @@
$date
Fri Sep 27 11:58:46 2024
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module tb $end
$var reg 4 ! a [3:0] $end
$var reg 4 " b [3:0] $end
$scope module uut $end
$var reg 4 # a [3:0] $end
$var reg 4 $ b [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b0001 !
b0001 "
b0001 #
b0001 $
#10000000

28
tests/sim/var_reference_without_whitespace.vcd Normal file
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@ -0,0 +1,28 @@
$date
Fri Sep 27 11:58:46 2024
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module tb $end
$var reg 4 ! a[3:0] $end
$var reg 4 " b[3:0] $end
$scope module uut $end
$var reg 4 # a[3:0] $end
$var reg 4 $ b[3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b0001 !
b0001 "
b0001 #
b0001 $
#10000000

3
tests/sim/vcd_var_reference_whitespace.ys Normal file
View File

@ -0,0 +1,3 @@
read_rtlil vector_assign.il
sim -r var_reference_without_whitespace.vcd -scope tb.uut
sim -r var_reference_with_whitespace.vcd -scope tb.uut

20
tests/sim/vector_assign.il Normal file
View File

@ -0,0 +1,20 @@
# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
autoidx 2
attribute \architecture "Behavioral"
attribute \library "work"
attribute \hdlname "vector_assign"
attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
module \vector_assign
attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
wire width 4 input 2 \a
attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
wire width 4 output 1 \b
attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \a
connect \Y \b
end
end