mirror of https://github.com/YosysHQ/yosys.git
functional, glift: use fold overload of IdString::in instead of pool literals
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799497ebba
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387a235158
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@ -253,7 +253,7 @@ public:
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int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
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bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
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bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
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if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul)})){
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if(cellType.in(ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul))){
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bool is_signed = a_signed && b_signed;
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Node a = factory.extend(inputs.at(ID(A)), y_width, is_signed);
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Node b = factory.extend(inputs.at(ID(B)), y_width, is_signed);
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@ -273,14 +273,14 @@ public:
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return factory.bitwise_not(factory.bitwise_xor(a, b));
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else
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log_abort();
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}else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){
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}else if(cellType.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt))){
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bool is_signed = a_signed && b_signed;
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int width = max(a_width, b_width);
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Node a = factory.extend(inputs.at(ID(A)), width, is_signed);
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Node b = factory.extend(inputs.at(ID(B)), width, is_signed);
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if(cellType.in({ID($eq), ID($eqx)}))
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if(cellType.in(ID($eq), ID($eqx)))
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return factory.extend(factory.equal(a, b), y_width, false);
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else if(cellType.in({ID($ne), ID($nex)}))
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else if(cellType.in(ID($ne), ID($nex)))
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return factory.extend(factory.not_equal(a, b), y_width, false);
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else if(cellType == ID($lt))
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return factory.extend(is_signed ? factory.signed_greater_than(b, a) : factory.unsigned_greater_than(b, a), y_width, false);
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@ -292,7 +292,7 @@ public:
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return factory.extend(is_signed ? factory.signed_greater_equal(a, b) : factory.unsigned_greater_equal(a, b), y_width, false);
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else
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log_abort();
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}else if(cellType.in({ID($logic_or), ID($logic_and)})){
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}else if(cellType.in(ID($logic_or), ID($logic_and))){
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Node a = factory.reduce_or(inputs.at(ID(A)));
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Node b = factory.reduce_or(inputs.at(ID(B)));
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Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
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@ -309,13 +309,13 @@ public:
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Node a = factory.reduce_or(inputs.at(ID(A)));
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Node y = factory.bitwise_not(a);
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return factory.extend(y, y_width, false);
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}else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){
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}else if(cellType.in(ID($reduce_or), ID($reduce_bool))){
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Node a = factory.reduce_or(inputs.at(ID(A)));
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return factory.extend(a, y_width, false);
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}else if(cellType == ID($reduce_and)){
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Node a = factory.reduce_and(inputs.at(ID(A)));
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return factory.extend(a, y_width, false);
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}else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){
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}else if(cellType.in(ID($reduce_xor), ID($reduce_xnor))){
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Node a = factory.reduce_xor(inputs.at(ID(A)));
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Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a;
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return factory.extend(y, y_width, false);
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@ -355,7 +355,7 @@ public:
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int offset = parameters.at(ID(OFFSET)).as_int();
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Node a = inputs.at(ID(A));
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return factory.slice(a, offset, y_width);
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}else if(cellType.in({ID($div), ID($mod), ID($divfloor), ID($modfloor)})) {
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}else if(cellType.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
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int width = max(a_width, b_width);
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bool is_signed = a_signed && b_signed;
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Node a = factory.extend(inputs.at(ID(A)), width, is_signed);
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@ -397,7 +397,7 @@ public:
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} else
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log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
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} else {
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if(cellType.in({ID($mod), ID($modfloor)}))
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if(cellType.in(ID($mod), ID($modfloor)))
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return factory.extend(factory.unsigned_mod(a, b), y_width, false);
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else
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return factory.extend(factory.unsigned_div(a, b), y_width, false);
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@ -439,12 +439,12 @@ public:
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return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI)));
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} else if(cellType == ID($alu)) {
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return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI)));
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} else if(cellType.in({ID($assert), ID($assume), ID($live), ID($fair), ID($cover)})) {
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} else if(cellType.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
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Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(ID(A)), inputs.at(ID(EN)));
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auto &output = factory.add_output(cellName, cellType, Sort(1));
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output.set_value(a);
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return {};
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} else if(cellType.in({ID($anyconst), ID($allconst), ID($anyseq), ID($allseq)})) {
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} else if(cellType.in(ID($anyconst), ID($allconst), ID($anyseq), ID($allseq))) {
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int width = parameters.at(ID(WIDTH)).as_int();
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auto &input = factory.add_input(cellName, cellType, Sort(width));
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return factory.value(input);
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@ -184,7 +184,7 @@ private:
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std::vector<RTLIL::SigSig> connections(module->connections());
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for(auto &cell : module->cells().to_vector()) {
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if (!cell->type.in({ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)}) && module->design->module(cell->type) == nullptr) {
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if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
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log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type.c_str());
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}
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if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
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