mirror of https://github.com/YosysHQ/yosys.git
parent
d629aa6bf1
commit
c98d134662
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@ -900,7 +900,7 @@ struct HelpPass : public Pass {
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fprintf(f, "%s\n", underline.c_str());
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// help text
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fprintf(f, "%s\n", cell.desc.c_str());
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fprintf(f, "%s\n\n", cell.desc.c_str());
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// source code
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fprintf(f, "Simulation model (Verilog)\n");
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