245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
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Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
bfacaddca8
show: Remove left-in debug log_warning
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-23 13:54:07 +01:00
bfc3c20cfb
Improve splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-01-18 00:31:29 +01:00
6574553189
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
f9e30ee5e0
passes: show: s/pos/bitpos/ for readability
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
314b864205
passes: show: Reuse string parts in generation of portboxes
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
61abca10a3
passes: show: Touch chunk iteration in gen_portbox
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
60318a5cd8
passes: show: Label no_signode flag
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Label the flag and rearrange the control flow a bit.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
8b1f5fba62
passes: show: Simplify wire bit range logic
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
ad149cc42a
passes: show: Factor out 'join_label_pieces'
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In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
5848790835
passes: show: Label signed_suffix flag
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To make it easier to follow what's going on.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
13700e12e5
passes: show: s/idx/dot_idx/ for readability
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Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
e3709ce776
passes: show: Fix portbox bit ranges in case of driven signals
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When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.
So, taking for example the following Verilog snippet,
module DRIVER (Q);
output [7:0] Q;
assign Q = 8'b10101010;
endmodule
module main;
wire w;
DRIVER driver(.Q({8{w}}));
endmodule
make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
5042600c0d
xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
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This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
2023-01-11 18:07:16 +01:00
4173daa708
Merge pull request #3605 from gadfort/stat-json-area
2023-01-11 16:41:44 +01:00
843f329b96
Merge branch 'master' into claire/eqystuff
2023-01-11 16:33:08 +01:00
5abaa59080
Merge pull request #3537 from jix/xprop
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New xprop pass
2023-01-11 16:26:04 +01:00
5801152779
Deprecate gcc-4.8
2023-01-11 09:54:19 +01:00
6d56d4ecfc
Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
2023-01-11 04:10:12 +01:00
58cca9592d
stat: ensure area is included in json output
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Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
2022-12-29 21:51:46 -05:00
4a0ed35aab
xprop: Improve signal splitting code
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Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
2022-12-12 17:51:01 +01:00
6a6e1d8424
Improvements in "viz" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-09 18:28:17 +01:00
3454bddbe2
Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff
2022-12-08 20:06:23 +01:00
172a8e79f0
xprop: Add -split-public option
2022-12-08 20:00:01 +01:00
068031d2aa
Improvements in "viz" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 16:10:58 +01:00
aeba966475
Improvements in "viz" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 12:46:49 +01:00
c679b408cb
Various improvements in "viz" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:43:01 +01:00
2895a66784
Bugfix in splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:00:48 +01:00
e151e44caa
Improvements in "viz" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 19:32:31 +01:00
c9f4b06cb2
Add "viz" pass for visualizing big-picture data flow in larger designs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 11:35:10 +01:00
92fc6cd4a9
Add splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 01:33:04 +01:00
7036a312bf
stat: Fix JSON output for empty designs
2022-12-02 14:36:19 +01:00
ed02d52f30
tee: Allow logging command output to a given scratchpad value
2022-12-02 14:36:19 +01:00
ce708122a5
New xprop pass to encode 3-valued x-propagation using 2-valued logic
2022-11-30 19:01:28 +01:00
a14dec79eb
Rst docs conversion ( #3496 )
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Rst docs conversion
2022-11-15 12:55:22 +01:00
69787f1906
remove extra space in formating
2022-09-22 15:46:36 +01:00
bc1e579483
stat: add tech tech-specific utilizations to json
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- refactor resource util. estimation/calculations for Xilinx and CMOS
- don't print log_header if "-json" is set
2022-09-22 15:46:36 +01:00
7d35003c16
Merge pull request #3449 from YosysHQ/aki/show_pathrw
2022-08-25 17:06:29 +02:00
9465b2af95
Fitting help messages to 80 character width
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Uses the regex below to search (using vscode):
^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);
Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
1433a63165
yosys: passes: cmds: show: added filename re-writing to `show -lib`
2022-08-22 06:04:54 -04:00
65145db7e7
rename: Add -witness mode
2022-08-16 13:37:30 +02:00
0cdb14df41
setundef: Do not add anyseq / anyconst to unused memory port clocks
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Instead set those unused clocks to zero.
2022-08-16 13:37:30 +02:00
c0063288d6
Add the $anyinit cell and the formalff pass
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These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json
2022-08-11 17:00:54 +02:00
59facfa98c
stat: add option for machine-readable json output
2022-08-11 13:41:01 +01:00
a48dcd1d40
rename: add -scramble-name option to randomly rename selections
2022-08-08 16:03:28 +01:00
5dfad5101d
chformal: Rename -coverprecond to -coverenable
2022-06-18 18:28:12 +01:00
e39c422734
chformal: Test -coverprecond and reuse the src attribute
2022-06-18 18:19:26 +01:00
c659bd1878
chformal: Add -coverprecond option
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This inserts $cover cells to cover the enable signal (precondition)
for the selected formal cells.
2022-06-18 18:19:26 +01:00
3eaa9e38e0
Merge pull request #3196 from bfg86/bfg86/rename
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Add -suffix option to rename -wire
2022-06-13 16:00:04 +02:00
aedd3b7999
Updating help-text with nakengelhardts suggestion.
2022-06-13 09:35:10 +02:00
b8ede6162b
Merge pull request #3349 from nakengelhardt/select_count_scratchpad
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Make 'stat' and 'select -count' save counts to scratchpad
2022-06-09 17:15:02 +02:00
aae2c01326
sta: warn on unrecognised cells only once
2022-06-08 09:31:49 +01:00
d88a5d26b7
Fix preventing show crashing with newer graphviz
2022-06-03 08:38:16 +02:00
61b05051e1
also make 'stat' save counts to scratchpad
2022-06-01 16:01:07 +02:00
a55c3db384
have 'select -count' save the count to scratchpad entry 'select.count'
2022-06-01 14:39:33 +02:00
fc65ea47df
select: Fix -assert-none and -assert-any error output and docs
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Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.
This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).
It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
2022-05-19 14:07:34 +02:00
0aec79a0da
show: Fix width labels.
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See #3266 .
2022-04-04 22:48:09 +02:00
e016518866
Merge pull request #2019 from boqwxp/glift
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Add `glift` command for creating gate-level information flow tracking models and optimization problems
2022-02-11 15:51:24 +01:00
7ac98d1c87
Add -suffix option to rename -wire.
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See #3195
2022-02-11 00:05:13 +01:00
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
4f1d62d9b2
bugpoint: avoid infinite loop between -connections and -wires.
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Fixes #3113 .
2021-12-15 08:17:02 +00:00
0aad88a2fb
Add clean_zerowidth pass, use it for Verilog output.
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This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.
See #3103 .
2021-12-12 19:56:50 +01:00
77327b2544
sta: very crude static timing analysis pass
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
107aad2cd2
show: Fix wire bit indexing.
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Fixes #3078 .
2021-11-12 15:09:58 +01:00
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
c58ac63c97
logger: Add -check-expected subcommand.
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This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
2021-08-12 17:41:39 +02:00
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
009940f56c
rtlil: Make Process handling more uniform with Cell and Wire.
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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
2021-07-12 00:47:34 +02:00
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
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Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
d9f11bb7a6
autoname: simple perf optimizations
2021-06-08 15:02:42 -04:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
c4cc888b2c
kernel/rtlil: Extract some helpers for checking memory cell types.
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There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
a6081b46ce
connect: Add -assert option, fix non-working sigmap.
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Should be useful for writing tests.
2021-05-08 15:49:41 +02:00
4c39189b13
Clarify bugpoint documentation regarding output
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Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice.
Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
2021-03-24 16:24:33 -05:00
c8b45a4a82
bugpoint: add runner option
2021-03-17 15:54:00 -04:00
dd6d34f461
blackbox: Include whiteboxed modules
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
74dad5afe7
scc: Add -specify option to find loops in boxes
2021-01-26 16:23:08 +00:00
e61b107072
plugin: enhance no-plugin error
2020-12-29 05:50:04 +01:00
1838edf35c
bugpoint: add -wires option.
2020-12-07 09:24:35 +00:00
2b474a01e1
bugpoint: try to remove whole processes first.
2020-12-07 08:42:54 +00:00
b1135a88dd
bugpoint: accept quoted strings in -grep.
2020-12-07 08:42:54 +00:00
75f9e9cb45
bugpoint: add -command option.
2020-12-07 08:42:54 +00:00
d6a93b8b90
check: add support for processes.
2020-11-03 15:36:27 +00:00
191406f930
check: reformat log/help text to match most other passes
2020-11-03 12:37:02 +00:00
3238190797
use the new isPublic() in a few places
2020-09-14 12:43:18 +02:00
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
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The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
bbfa2d65fa
glift: Use ID() rather than string literals.
2020-07-01 19:51:48 +00:00
eda1af73c4
glift: Use worker pattern.
2020-07-01 19:51:47 +00:00
3eb2593876
glift: Add support for $_NAND_ and $_NOR_ cells.
2020-07-01 19:51:47 +00:00
8cb1a86c23
glift: Add support for $_MUX_ and $_NMUX_ cells.
2020-07-01 19:51:47 +00:00
23defc6fe9
glift: Add support for $_XOR_ and $_XNOR_ cells.
2020-07-01 19:51:47 +00:00
209a123b97
glift: Add initial hierarchy support.
2020-07-01 19:51:47 +00:00
20ad371724
glift: Replace `YS_OVERRIDE` with `override`.
2020-07-01 19:51:47 +00:00
91c20fca72
glift: Add `-simple-cost-model` option
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Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell:
- 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell
- 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell
This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem.
2020-07-01 19:51:47 +00:00
26bd686259
glift: Add `-instrument-more` option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text.
2020-07-01 19:51:46 +00:00
bc207d5426
glift: Change command names to better represent their functions.
2020-07-01 19:51:46 +00:00
ddfb9f08e2
glift: Add `-create-imprecise` command, rename other commands, and re-work the help text.
2020-07-01 19:51:46 +00:00
72cebef279
glift: Add replacement scoring and area minimization option.
2020-07-01 19:51:46 +00:00
Miodrag Milanović
gatecat
Claire Xenia Wolf
Martin Povišer
Jannis Harder
N. Engelhardt
Peter Gadfort
KrystalDelusion
Kamyar Mohajerani
KrystalDelusion
Aki Van Ness
Lofty
George Rennie
bfg86
Marcelina Kościelnicka
Catherine
Zachary Snow
Iris Johnson
umarcor
N. Engelhardt
Alberto Gonzalez