abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
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ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
35990b95ec
Extend support for format strings in Verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
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The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
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ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
9b4dab397e
Fix 5bba9c3, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
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duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
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Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
d22888ce74
read_ilang: improve error message for overly long wires.
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Fixes #1838 .
2020-04-06 10:33:02 +00:00
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
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ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
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Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
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verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
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Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
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Fix NDEBUG warnings
2020-03-19 14:58:06 -07:00
whitequark
Claire Wolf
Alberto Gonzalez
David Shah
Henner Zeller
Jeff Wang
Eddie Hung
Claire Wolf
Diego H
N. Engelhardt
Peter Crozier
Rupert Swarbrick