riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
875 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

875 Commits

Author SHA1 Message Date
Clifford Wolf 0defc86519 renamed ilang "scope error" to "ilang error" 2014-02-11 19:17:07 +01:00
Clifford Wolf d2fd45949d More Makefile cleanups 2014-02-11 12:58:08 +01:00
Clifford Wolf 4bd2d47e45 Improved "make manual" and "make clean" 2014-02-11 12:55:58 +01:00
Clifford Wolf fb186e6299 Improved ilang parser error messages 2014-02-09 15:35:31 +01:00
Clifford Wolf d229324420 fixed a bug in subcircuit library with cells that have connections to itself 2014-02-09 15:27:58 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
Clifford Wolf b6f33576d5 Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
Clifford Wolf b3b5fac191 Bugfix in delete command 2014-02-09 09:34:58 +01:00
Clifford Wolf 039bb456cc Added test cases for expose -evert-dff 2014-02-08 21:31:56 +01:00
Clifford Wolf 85914c36e5 Fixed handling of async reset in expose -evert-dff 2014-02-08 21:26:40 +01:00
Clifford Wolf db86aaa07d Build fixes for log cmd 2014-02-08 21:21:51 +01:00
Clifford Wolf c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-08 21:08:46 +01:00
Clifford Wolf 0935e20003 Implemented expose -evert-dff 2014-02-08 21:08:38 +01:00
Clifford Wolf 793290a304 Merge pull request #24 from hansiglaser/master 
added "log" command
 2014-02-08 20:02:32 +01:00
Johann Glaser af14bb5f65 added "log" command 2014-02-08 19:19:32 +01:00
Clifford Wolf 8f9c707a4c Improved checking of internal cell conventions 2014-02-08 19:13:49 +01:00
Clifford Wolf 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
Clifford Wolf 926fa61119 Added various new options to splice command 2014-02-08 16:37:18 +01:00
Clifford Wolf 0c11d04144 Added %a select operator 2014-02-08 16:31:38 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf 03ee63ff80 Added support for "keep" attribute to abc pass 2014-02-08 14:25:29 +01:00
Clifford Wolf 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
Clifford Wolf 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean 2014-02-08 14:21:04 +01:00
Clifford Wolf 669a6e462d Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output 2014-02-08 12:27:38 +01:00
Clifford Wolf 2c51619c2b Now also move net labes to the right position in splice cmd 2014-02-08 00:06:00 +01:00
Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean 2014-02-07 23:50:17 +01:00
Clifford Wolf 244e8ce1f4 Added splice command 2014-02-07 20:30:56 +01:00
Clifford Wolf 08aa1062b4 Added log_header() to splitnets 2014-02-07 19:51:15 +01:00
Clifford Wolf d85a6bf5d3 Added $slice and $concat to CellTypes list 2014-02-07 19:50:44 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf a1ac710ab8 Stronger checking of internal cells 2014-02-07 17:39:35 +01:00
Clifford Wolf 99b1e9ee56 Re-enabled abc "retime" after sorting yout the yosys-bigsim problem 2014-02-07 16:36:37 +01:00
Clifford Wolf a51a3fa2d2 Added echo command 2014-02-07 14:17:00 +01:00
Clifford Wolf 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc 2014-02-07 14:16:42 +01:00
Clifford Wolf f4f230d7cc Fixed gcc compiler warnings with release build 2014-02-06 22:49:14 +01:00
Clifford Wolf 0192f1c66e Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed) 2014-02-06 22:31:58 +01:00
Clifford Wolf a170d114a5 Updated ABC to rev 10cc13a2a0f1 2014-02-06 22:18:17 +01:00
Clifford Wolf 58cb8d65af Added "retime" to standard ABC recipes 2014-02-06 22:16:20 +01:00
Clifford Wolf 91eab69912 Added copy command 2014-02-06 22:09:21 +01:00
Clifford Wolf cf593222f2 Added design -stash/-copy-from/-copy-to 2014-02-06 21:52:07 +01:00
Clifford Wolf 37fdb2ca7a Added support for s: select expressions (wire width) 2014-02-06 19:45:03 +01:00
Clifford Wolf 9428050dd6 Added i:, o:, and x: selection pattern 2014-02-06 19:35:33 +01:00
Clifford Wolf d7d1c7baf8 Added support for %m selection op 2014-02-06 19:30:08 +01:00
Clifford Wolf f2fdcef13d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-06 19:22:50 +01:00
Clifford Wolf fa295a4528 Added generic RTLIL::SigSpec::parse_sel() with support for selection variables 2014-02-06 19:22:46 +01:00
Clifford Wolf 9c24b41f55 Merge pull request #23 from hansiglaser/master 
new %s: add sub-modules to selection
 2014-02-06 18:08:02 +01:00
Johann Glaser 34eb77d2bf new %s: add sub-modules to selection 2014-02-06 17:36:39 +01:00
Clifford Wolf d4b0f28881 Added support for sat -show @<sel_name> 2014-02-06 17:32:51 +01:00
Clifford Wolf b1a12c5f37 Added sat -set-init-def and sat -tempinduct-def 2014-02-06 16:15:23 +01:00
Clifford Wolf 594d52e0b6 Added opt_const -undriven 2014-02-06 15:49:03 +01:00