c58bb1d2e1
ast: make design available to process_module()
2021-03-24 10:21:00 -04:00
8740fdf1d7
ast: Use better parameter serialization for paramod names.
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Calling log_signal is problematic for several reasons:
- with recent changes, empty string is serialized as { }, which violates
the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
functionally different values and potentially introducing a subtle
elaboration bug
Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
640b9927fa
sv: allow globals in one file to depend on globals in another
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This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
cb9f3b6abf
verilog: disallow overriding global parameters
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It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
26e01a67db
Merge pull request #2643 from zachjs/fix-param-no-default-log
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Fix param without default log line
2021-03-08 16:36:03 -08:00
89c74ffd71
verilog: Use proc memory writes in the frontend.
2021-03-08 20:16:29 +01:00
bdc4fd0e92
Fix param without default log line
2021-03-07 16:06:25 -05:00
9bb839c613
Merge pull request #2626 from zachjs/param-no-default
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sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
b1a8e73a60
sv: fix some edge cases for unbased unsized literals
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
d738b2c127
sv: support for parameters without default values
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- Modules with a parameter without a default value will be automatically
deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
f4f471f342
frontend: Make helper functions for printing locations.
2021-02-23 23:51:52 +01:00
a4c04d1b90
ast: fix dump_vlog display of casex/casez
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The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
2021-01-29 16:28:15 +01:00
2e23dfd96b
Return correct modname when found in cache.
2020-11-26 13:31:22 +01:00
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
185bbbe681
static cast: support changing size and signedness
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Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
2020-06-19 17:39:20 -07:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
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The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
e79376d6cb
ast: quiet down when deriving blackbox modules
2020-02-27 10:17:29 -08:00
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
0a1af434e8
Fix for svinterfaces
2019-09-30 14:52:04 -07:00
08b55a20e3
module->derive() to be lazy and not touch ast if already derived
2019-09-30 14:11:01 -07:00
8da0888bf6
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 12:16:20 +02:00
83ffec26cb
Remove newline
2019-08-29 09:08:58 -07:00
6510297712
Restore non-deferred code, deferred case to ignore non constant attr
2019-08-29 09:02:10 -07:00
34ae29295d
read_verilog -defer should still populate module attributes
2019-08-28 19:59:09 -07:00
24971fda87
handle real values when deriving ast modules
2019-08-19 14:17:36 +02:00
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310f54bf1631f
2019-08-12 12:06:45 -07:00
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Zachary Snow
Marcelina Kościelnicka
whitequark
Julius Roob
Udi Finkelstein
Kazuki Sakamoto
Peter Crozier
Claire Wolf
Claire Wolf
David Shah
Eddie Hung
Alberto Gonzalez
Jeff Wang
Jakob Wenzel
David Shah