Clifford Wolf
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921064c200
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Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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a2d053694b
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Fix in sincos testbench gen
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2013-12-04 09:24:52 +01:00 |
Clifford Wolf
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d1517b7982
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Added sincos test case
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2013-12-04 09:10:41 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
Clifford Wolf
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c5e26f839c
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Added additional mem2reg testcase
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2013-11-18 19:55:39 +01:00 |
Clifford Wolf
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2a25e3bca3
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
Clifford Wolf
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fc6dc0d7b8
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
Clifford Wolf
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628b994cf6
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Added support for complex set-reset flip-flops in proc_dff
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2013-10-24 16:54:05 +02:00 |
Clifford Wolf
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d61699843f
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Improved handling of dff with async resets
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2013-10-21 14:51:58 +02:00 |
Clifford Wolf
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759852914d
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
Clifford Wolf
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3650fd7fbe
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More fixes in ternary op sign handling
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2013-07-12 13:13:04 +02:00 |
Clifford Wolf
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ded769c98c
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Fixed sign handling in ternary operator
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2013-07-12 01:15:37 +02:00 |
Clifford Wolf
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b380c8c790
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Another vloghammer related bugfix
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2013-07-11 19:24:59 +02:00 |
Clifford Wolf
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5dab327b30
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More fixes in ast expression sign/width handling
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2013-07-09 23:41:43 +02:00 |
Clifford Wolf
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618b2ac994
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-07-09 19:00:10 +02:00 |
Clifford Wolf
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7daeee340a
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Fixed shift ops with large right hand side
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2013-07-09 18:59:59 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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e8da3ea7b6
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Fixed another bug found using vloghammer
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2013-07-07 16:49:30 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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e0c408cb4a
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
Clifford Wolf
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5640b7d607
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
Clifford Wolf
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d9bc024d29
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Renamed hansimem.v test case to mem_arst.v
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2013-03-24 15:25:08 +01:00 |
Clifford Wolf
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c3c9e5a02f
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Added hansimem testcase (memory with async reset)
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2013-03-24 10:40:40 +01:00 |
Johann Glaser
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3cfbc18601
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added ckeck for Icarus Verilog, otherwise the tests are silently stopped
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2013-03-17 09:05:15 +01:00 |
Clifford Wolf
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2d9cbd3b02
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |