2013-01-05 04:13:26 -06:00
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OBJS += passes/techmap/techmap.o
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2013-11-24 15:52:30 -06:00
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OBJS += passes/techmap/simplemap.o
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2013-10-16 08:32:26 -05:00
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OBJS += passes/techmap/dfflibmap.o
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2014-12-30 04:41:24 -06:00
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OBJS += passes/techmap/maccmap.o
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2014-07-24 12:03:57 -05:00
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OBJS += passes/techmap/libparse.o
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2015-05-17 07:44:28 -05:00
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ifeq ($(ENABLE_ABC),1)
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|
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OBJS += passes/techmap/abc.o
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2019-02-08 15:58:47 -06:00
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OBJS += passes/techmap/abc9.o
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2020-01-06 17:52:59 -06:00
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OBJS += passes/techmap/abc9_exe.o
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2019-12-28 07:07:46 -06:00
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OBJS += passes/techmap/abc9_ops.o
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2016-03-19 14:02:40 -05:00
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ifneq ($(ABCEXTERNAL),)
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passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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2019-06-28 13:54:58 -05:00
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passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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2020-01-30 14:12:43 -06:00
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passes/techmap/abc9_exe.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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2016-03-19 14:02:40 -05:00
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endif
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2015-05-17 07:44:28 -05:00
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endif
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2014-07-24 12:03:57 -05:00
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ifneq ($(SMALL),1)
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2013-10-16 09:16:06 -05:00
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OBJS += passes/techmap/iopadmap.o
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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|
|
OBJS += passes/techmap/clkbufmap.o
|
2014-01-19 14:58:58 -06:00
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|
OBJS += passes/techmap/hilomap.o
|
2014-02-08 07:39:15 -06:00
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|
OBJS += passes/techmap/extract.o
|
2017-08-25 05:04:40 -05:00
|
|
|
OBJS += passes/techmap/extract_fa.o
|
2017-08-28 22:52:08 -05:00
|
|
|
OBJS += passes/techmap/extract_counter.o
|
2017-08-28 12:52:06 -05:00
|
|
|
OBJS += passes/techmap/extract_reduce.o
|
2014-09-14 03:02:00 -05:00
|
|
|
OBJS += passes/techmap/alumacc.o
|
2014-12-08 07:10:52 -06:00
|
|
|
OBJS += passes/techmap/dff2dffe.o
|
2015-04-04 12:00:15 -05:00
|
|
|
OBJS += passes/techmap/dffinit.o
|
2015-04-07 13:27:10 -05:00
|
|
|
OBJS += passes/techmap/pmuxtree.o
|
2015-04-07 08:42:25 -05:00
|
|
|
OBJS += passes/techmap/muxcover.o
|
2015-06-10 00:24:26 -05:00
|
|
|
OBJS += passes/techmap/aigmap.o
|
2015-08-16 05:55:25 -05:00
|
|
|
OBJS += passes/techmap/tribuf.o
|
2015-09-18 14:55:48 -05:00
|
|
|
OBJS += passes/techmap/lut2mux.o
|
2015-09-18 14:57:34 -05:00
|
|
|
OBJS += passes/techmap/nlutmap.o
|
2016-02-02 10:19:01 -06:00
|
|
|
OBJS += passes/techmap/dffsr2dff.o
|
2016-04-16 16:20:49 -05:00
|
|
|
OBJS += passes/techmap/shregmap.o
|
2016-06-19 06:08:16 -05:00
|
|
|
OBJS += passes/techmap/deminout.o
|
2016-08-02 03:37:19 -05:00
|
|
|
OBJS += passes/techmap/insbuf.o
|
2016-08-09 04:18:48 -05:00
|
|
|
OBJS += passes/techmap/attrmvcp.o
|
2016-08-09 12:56:55 -05:00
|
|
|
OBJS += passes/techmap/attrmap.o
|
2016-10-12 05:05:19 -05:00
|
|
|
OBJS += passes/techmap/zinit.o
|
2018-07-14 08:54:30 -05:00
|
|
|
OBJS += passes/techmap/dff2dffs.o
|
2019-01-02 08:09:53 -06:00
|
|
|
OBJS += passes/techmap/flowmap.o
|
2019-08-28 09:58:14 -05:00
|
|
|
OBJS += passes/techmap/extractinv.o
|
2014-07-24 12:03:57 -05:00
|
|
|
endif
|
2013-10-16 08:32:26 -05:00
|
|
|
|
2014-07-30 19:32:00 -05:00
|
|
|
GENFILES += passes/techmap/techmap.inc
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-30 19:32:00 -05:00
|
|
|
passes/techmap/techmap.inc: techlibs/common/techmap.v
|
2015-08-12 08:04:44 -05:00
|
|
|
$(Q) mkdir -p $(dir $@)
|
2014-07-24 10:15:01 -05:00
|
|
|
$(P) echo "// autogenerated from $<" > $@.new
|
|
|
|
$(Q) echo "static char stdcells_code[] = {" >> $@.new
|
|
|
|
$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
|
|
|
|
$(Q) echo "0};" >> $@.new
|
|
|
|
$(Q) mv $@.new $@
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-30 19:32:00 -05:00
|
|
|
passes/techmap/techmap.o: passes/techmap/techmap.inc
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2015-02-15 05:09:30 -06:00
|
|
|
ifneq ($(CONFIG),emcc)
|
2014-10-09 03:50:44 -05:00
|
|
|
TARGETS += yosys-filterlib$(EXE)
|
2014-10-17 05:11:15 -05:00
|
|
|
EXTRA_OBJS += passes/techmap/filterlib.o
|
2013-10-16 08:32:26 -05:00
|
|
|
|
2014-10-09 03:50:44 -05:00
|
|
|
yosys-filterlib$(EXE): passes/techmap/filterlib.o
|
2015-08-12 08:04:44 -05:00
|
|
|
$(Q) mkdir -p $(dir $@)
|
2016-01-31 12:55:48 -06:00
|
|
|
$(P) $(LD) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
|
2015-02-15 05:09:30 -06:00
|
|
|
endif
|