2016-11-12 15:33:28 -06:00
yosys – Yosys Open SYnthesis Suite
2013-01-05 04:13:26 -06:00
===================================
2013-02-28 07:17:57 -06:00
This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.
2013-01-05 04:13:26 -06:00
2013-02-28 07:17:57 -06:00
Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
2013-03-16 15:20:38 -05:00
adding additional passes as needed by extending the yosys C++
code base.
2013-01-05 04:13:26 -06:00
Yosys is free software licensed under the ISC license (a GPL
2013-03-16 15:20:38 -05:00
compatible license that is similar in terms to the MIT license
2013-01-05 04:13:26 -06:00
or the 2-clause BSD license).
2024-10-16 17:11:10 -05:00
Third-party software distributed alongside this software
is licensed under compatible licenses.
Please refer to `abc` and `libs` subdirectories for their license terms.
2013-01-05 04:13:26 -06:00
2024-12-04 14:21:13 -06:00
2019-03-01 16:29:17 -06:00
Web Site and Other Resources
============================
2013-07-21 08:04:37 -05:00
More information and documentation can be found on the Yosys web site:
2021-06-09 05:16:56 -05:00
- https://yosyshq.net/yosys/
2019-03-01 16:29:17 -06:00
2024-12-04 14:21:13 -06:00
Documentation from this repository is automatically built and available on Read
the Docs:
- https://yosyshq.readthedocs.io/projects/yosys
Users interested in formal verification might want to use the formal
verification front-end for Yosys, SBY:
- https://yosyshq.readthedocs.io/projects/sby/
- https://github.com/YosysHQ/sby
2019-03-01 16:29:17 -06:00
2013-07-21 08:04:37 -05:00
2022-01-04 08:44:37 -06:00
Installation
============
Yosys is part of the [Tabby CAD Suite ](https://www.yosyshq.com/tabby-cad-datasheet ) and the [OSS CAD Suite ](https://github.com/YosysHQ/oss-cad-suite-build )! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.
* [Contact YosysHQ ](https://www.yosyshq.com/contact ) for a [Tabby CAD Suite ](https://www.yosyshq.com/tabby-cad-datasheet ) Evaluation License and download link
* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
* Follow the [Install Instructions on GitHub ](https://github.com/YosysHQ/oss-cad-suite-build#installation )
Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!
For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
2022-01-17 05:49:32 -06:00
Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!
2022-01-04 08:44:37 -06:00
2024-12-04 14:21:13 -06:00
2022-01-04 08:44:37 -06:00
Building from Source
====================
2013-01-06 07:40:15 -06:00
2024-12-04 14:21:13 -06:00
For more details, and instructions for other platforms, check [building from
source](https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_started/installation.html#building-from-source)
on Read the Docs.
When cloning Yosys, some required libraries are included as git submodules. Make
sure to call e.g.
$ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git
or
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys
$ git submodule update --init --recursive
2024-06-17 10:08:13 -05:00
You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is
2013-10-11 15:25:23 -05:00
recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
2017-02-04 10:02:13 -06:00
TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
2016-11-19 10:34:13 -06:00
Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
2017-02-07 08:12:31 -06:00
2016-09-03 11:49:53 -05:00
For example on Ubuntu Linux 16.04 LTS the following commands will install all
2014-09-01 20:52:46 -05:00
prerequisites for building yosys:
2024-07-22 14:33:46 -05:00
$ sudo apt-get install build-essential clang lld bison flex \
2018-05-15 07:19:05 -05:00
libreadline-dev gawk tcl-dev libffi-dev git \
2019-04-03 04:18:34 -05:00
graphviz xdot pkg-config python3 libboost-system-dev \
2019-07-26 04:23:58 -05:00
libboost-python-dev libboost-filesystem-dev zlib1g-dev
2014-04-18 03:19:46 -05:00
2024-03-07 16:09:03 -06:00
The environment variable `CXX` can be used to control the C++ compiler used, or
2024-12-04 14:21:13 -06:00
run one of the following to override it:
2013-03-18 13:26:35 -05:00
2014-09-01 20:52:46 -05:00
$ make config-clang
$ make config-gcc
2013-03-18 13:26:35 -05:00
2024-08-05 12:28:09 -05:00
The Makefile has many variables influencing the build process. These can be
2024-12-04 14:21:13 -06:00
adjusted by modifying the Makefile.conf file which is created at the `make
config-...` step (see above), or they can be set by passing an option to the
make command directly:
2024-10-22 05:45:06 -05:00
2024-12-04 14:21:13 -06:00
$ make CXX=$CXX
2024-10-22 05:45:06 -05:00
2024-12-04 14:21:13 -06:00
For other compilers and build configurations it might be necessary to make some
changes to the config section of the Makefile. It's also an alternative way to
set the make variables mentioned above.
2013-01-06 07:40:15 -06:00
2016-11-12 15:33:28 -06:00
$ vi Makefile # ..or..
2014-04-18 03:19:46 -05:00
$ vi Makefile.conf
2013-03-18 13:26:35 -05:00
To build Yosys simply type 'make' in this directory.
2013-01-06 07:40:15 -06:00
$ make
$ sudo make install
2024-12-04 14:21:13 -06:00
Tests are located in the tests subdirectory and can be executed using the test
target. Note that you need gawk as well as a recent version of iverilog (i.e.
build from git). Then, execute tests via:
2019-03-16 07:20:59 -05:00
$ make test
2020-04-24 13:07:13 -05:00
To use a separate (out-of-tree) build directory, provide a path to the Makefile.
$ mkdir build; cd build
$ make -f ../Makefile
Out-of-tree builds require a clean source tree.
2024-12-04 14:21:13 -06:00
2017-02-07 08:12:31 -06:00
Getting Started
===============
2013-03-16 15:20:38 -05:00
Yosys can be used with the interactive command shell, with
synthesis scripts or with command line arguments. Let's perform
2013-01-06 07:40:15 -06:00
a simple synthesis job using the interactive command shell:
$ ./yosys
yosys>
2016-11-19 10:34:13 -06:00
the command ``help`` can be used to print a list of all available
commands and ``help < command > `` to print details on the specified command:
2013-02-28 07:17:57 -06:00
yosys> help help
2019-07-29 03:40:30 -05:00
reading and elaborating the design using the Verilog frontend:
2013-01-06 07:40:15 -06:00
2019-07-29 03:40:30 -05:00
yosys> read -sv tests/simple/fiedler-cooley.v
yosys> hierarchy -top up3down5
2013-01-06 07:40:15 -06:00
2023-07-10 05:54:02 -05:00
writing the design to the console in the RTLIL format used by Yosys
internally:
2013-01-06 07:40:15 -06:00
2023-07-10 05:54:02 -05:00
yosys> write_rtlil
2013-01-06 07:40:15 -06:00
2016-11-19 10:34:13 -06:00
convert processes (``always`` blocks) to netlist elements and perform
2013-01-06 07:40:15 -06:00
some simple optimizations:
yosys> proc; opt
2016-11-19 10:34:13 -06:00
display design netlist using ``xdot``:
2013-01-06 07:40:15 -06:00
2013-04-27 07:41:46 -05:00
yosys> show
2016-11-19 10:34:13 -06:00
the same thing using ``gv`` as postscript viewer:
2013-04-27 07:41:46 -05:00
yosys> show -format ps -viewer gv
2013-01-06 07:40:15 -06:00
translating netlist to gate logic and perform some simple optimizations:
yosys> techmap; opt
2015-08-14 15:23:01 -05:00
write design netlist to a new Verilog file:
2013-01-06 07:40:15 -06:00
yosys> write_verilog synth.v
or using a simple synthesis script:
$ cat synth.ys
2019-07-29 03:40:30 -05:00
read -sv tests/simple/fiedler-cooley.v
hierarchy -top up3down5
proc; opt; techmap; opt
2013-01-06 07:40:15 -06:00
write_verilog synth.v
2013-01-16 10:32:11 -06:00
$ ./yosys synth.ys
2013-01-06 07:40:15 -06:00
2013-12-08 08:42:27 -06:00
If ABC is enabled in the Yosys build configuration and a cell library is given
2016-11-19 12:51:50 -06:00
in the liberty file ``mycells.lib``, the following synthesis script will
synthesize for the given cell library:
2013-01-06 07:40:15 -06:00
2019-07-29 03:40:30 -05:00
# read design
read -sv tests/simple/fiedler-cooley.v
hierarchy -top up3down5
2013-01-06 07:40:15 -06:00
# the high-level stuff
2019-07-29 03:40:30 -05:00
proc; fsm; opt; memory; opt
2013-01-06 07:40:15 -06:00
# mapping to internal cell library
2013-02-28 07:17:57 -06:00
techmap; opt
2013-01-06 07:40:15 -06:00
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
2014-01-29 04:11:10 -06:00
clean
2013-01-06 07:40:15 -06:00
2013-10-31 05:15:00 -05:00
If you do not have a liberty file but want to test this synthesis script,
2019-07-29 03:40:30 -05:00
you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
as simple example.
2013-10-31 05:15:00 -05:00
2015-11-12 06:15:19 -06:00
Liberty file downloads for and information about free and open ASIC standard
cell libraries can be found here:
2014-06-28 05:11:42 -05:00
2016-11-12 15:33:28 -06:00
- http://www.vlsitechnology.org/html/libraries.html
- http://www.vlsitechnology.org/synopsys/vsclib013.lib
2014-06-28 05:11:42 -05:00
2016-11-19 12:51:50 -06:00
The command ``synth`` provides a good default synthesis script (see
2019-07-29 03:40:30 -05:00
``help synth``):
2014-09-14 09:09:06 -05:00
2019-07-29 03:40:30 -05:00
read -sv tests/simple/fiedler-cooley.v
synth -top up3down5
2014-09-14 09:09:06 -05:00
2019-07-29 03:40:30 -05:00
# mapping to target cells
2014-09-14 09:09:06 -05:00
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean
2019-07-29 03:40:30 -05:00
The command ``prep`` provides a good default word-level synthesis script, as
used in SMT-based formal verification.
2013-01-06 07:40:15 -06:00
2024-11-04 18:42:16 -06:00
Additional information
======================
The ``read_verilog`` command, used by default when calling ``read`` with Verilog
2024-11-08 09:30:06 -06:00
source input, does not perform syntax checking. You should instead lint your
source with another tool such as
2024-11-04 18:42:16 -06:00
[Verilator ](https://www.veripool.org/verilator/ ) first, e.g. by calling
``verilator --lint-only``.
2016-04-03 07:26:46 -05:00
Building the documentation
==========================
2016-05-09 05:43:49 -05:00
Note that there is no need to build the manual if you just want to read it.
2022-12-07 10:51:07 -06:00
Simply visit https://yosys.readthedocs.io/en/latest/ instead.
2016-05-09 05:43:49 -05:00
2022-12-07 10:51:07 -06:00
In addition to those packages listed above for building Yosys from source, the
following are used for building the website:
2022-11-15 05:55:22 -06:00
2023-08-02 16:20:24 -05:00
$ sudo apt install pdf2svg faketime
2022-11-15 05:55:22 -06:00
2024-08-22 19:53:38 -05:00
Or for MacOS, using homebrew:
$ brew install pdf2svg libfaketime
2022-11-15 05:55:22 -06:00
PDFLaTeX, included with most LaTeX distributions, is also needed during the
2023-08-02 16:20:24 -05:00
build process for the website. Or, run the following:
2023-08-27 17:09:34 -05:00
$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
2022-11-15 05:55:22 -06:00
2024-09-03 02:15:12 -05:00
Or for MacOS, using homebrew:
$ brew install basictex
$ sudo tlmgr update --self
$ sudo tlmgr install collection-latexextra latexmk tex-gyre
2022-11-15 05:55:22 -06:00
The Python package, Sphinx, is needed along with those listed in
`docs/source/requirements.txt` :
$ pip install -U sphinx -r docs/source/requirements.txt
From the root of the repository, run `make docs` . This will build/rebuild yosys
as necessary before generating the website documentation from the yosys help
commands. To build for pdf instead of html, call
`make docs DOC_TARGET=latexpdf` .