Commit Graph

135 Commits

Author SHA1 Message Date
Krystine Sherwin 0aef78245e
Moving primary build instructions to docs
Also drop visual studio instructions.
2024-12-05 09:21:13 +13:00
Krystine Sherwin 2bd53395fe
README: Some updating of web site section 2024-12-05 09:21:13 +13:00
Krystine Sherwin 9ee98c5da6
README: Drop the license from the top
Github shows the license file automatically, and the first section mentions it is ISC.
2024-12-05 09:21:13 +13:00
Krystine Sherwin 9925b27432
Goodbye guidelines (except GettingStarted)
Drop the parts that are being dropped.
Move the things that are being moved.
Also move the verilog stuff out of README and into the docs.
GettingStarted is less cut and dry, so hold off on that one.
2024-12-05 09:21:12 +13:00
Krystine Sherwin f0da1cc67f
Start removing guidelines folder
Disable the export to docs and remove any references to the guidelines folder.
2024-12-05 09:18:56 +13:00
Martin Povišer 109d97bb40
Merge pull request #4706 from povik/keep_hierarchy-adjustalgo
Adjust `keep_hierarchy` behavior
2024-12-03 12:18:28 +01:00
Martin Povišer f81dbf2433 Update `gate_cost_equivalent` help 2024-12-03 11:09:15 +01:00
KrystalDelusion 22e214ec6d
Merge pull request #4705 from YosysHQ/docs-preview-lintonly
Emphasise that read_verilog doesn't lint
2024-11-19 03:57:01 +13:00
Krystine Sherwin d0e5677760
Docs: Less exaggeration 2024-11-12 16:33:47 +13:00
Martin Povišer 426ef53c20 Document `gate_cost_equivalent` 2024-11-05 09:14:23 +01:00
Krystine Sherwin f2517f7599
README: Add note on linting 2024-11-05 13:42:16 +13:00
Emil J f3213d5057 README: tell macOS users to use brew clang with LTO 2024-10-22 12:47:37 +02:00
Emil J. Tywoniak d29499a10f actions: vendor sources with submodules for releases 2024-10-17 00:11:10 +02:00
Miodrag Milanovic 89cbca4f44 Add macOS instructions for latexpdf 2024-09-03 09:15:12 +02:00
Krystine Sherwin 7d63fdd88e
README: building docs on macos 2024-08-27 10:06:25 +12:00
Emil J. Tywoniak eeecb54532 Makefile: no LTO and lld by default 2024-08-05 19:28:09 +02:00
Emil J. Tywoniak a947572f38 Add lld to clang build environments and Dockerfile 2024-07-22 21:33:46 +02:00
Martin Povišer f9b7b8fff0 Update documentation for C++17 switch 2024-06-17 17:08:13 +02:00
Miodrag Milanović c9d9b9ec2c
Merge pull request #4270 from YosysHQ/krys/config-none
Change default CONFIG to none
2024-03-25 16:13:32 +01:00
Krystine Sherwin 56f66596b0
Change default CONFIG to none
- Use default value of `CXX` instead of forcing override to `clang++`.
- Add base `CXXFLAGS` and `ABCMKARGS` in else condition of `ifeq ($(CONFIG),..)`
  block and output the value of `CXX`.
- Change readme to mention `CXX` envvar and that using `make config-clang` etc
  will ignore `CXX`.
2024-03-09 10:25:41 +13:00
Krystine Sherwin 1455941ab9
Merge branch 'master' into krys/docs 2024-03-05 05:48:46 +13:00
Martin Povišer 173f4b5fbd Bump Claire's notices 2024-02-22 22:03:44 +01:00
Dag Lem fab326d3e8 Add multidimensional arrays to SystemVerilog features in README 2024-02-11 11:26:52 -05:00
Krystine Sherwin 8fad77bd0f
Merge branch 'master' into krys/docs
Fix failing verific tests
2023-11-01 13:17:51 +13:00
Zachary Snow 4edb1a1921 sv: support assignments within expressions
- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.
2023-09-05 22:27:55 -04:00
Krystine Sherwin 70c47690b3
Updating todo text and assorted fixes
Fix #3905 by removing emoji (and move the comment into the if block for less ambiguity).
Adds `latexmk` to README.

Note that latexpdf doesn't seem to like `cmd:ref` links, possibly because the
reference location is inside a latex comment block, but I was under the
impression that there was a reference location in there previously which was
working fine.  May be related to how the `cmd:def` block expands (or doesn't as
the case may be).
2023-08-28 10:09:43 +12:00
Krystine Sherwin 4f1cd66829
New structure headings
Also adds a note to readme for installing pdflatex if it's missing.
2023-08-03 09:20:24 +12:00
Martin Povišer 0d5e9acd34 README.md: s/write_ilang/write_rtlil/
It's my understanding write_ilang is deprecated so best no to mention it
in the README.
2023-07-10 12:57:05 +02:00
KrystalDelusion 4b95fac139 Removing old manual from README.md 2022-12-08 05:51:07 +13:00
KrystalDelusion b9b5899cce
Remove docs dependency on yosys repo (#3558)
* Copies guidelines files into docs/ for website

* Copying manual/CHAPTER_Prog for new docs

* Copying manual/APPNOTE_011... for new docs

Also adding faketime to list of packages for website build.

Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
2022-11-24 15:56:44 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496)
Rst docs conversion
2022-11-15 12:55:22 +01:00
Jannis Harder 5343911263 Mention smtlib2_module in README.md and CHANGELOG 2022-07-04 13:54:49 +02:00
N. Engelhardt 15b4d05805 mention distributions' package manager 2022-01-17 12:49:32 +01:00
N. Engelhardt 6483e691bc mention tabby+oss cad suite in readme 2022-01-04 15:44:37 +01:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
N. Engelhardt d9ec35a526 split CodingReadme into multiple files 2021-03-22 19:16:25 +01:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Peter Crozier 0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Claire Wolf bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
whitequark 9b26a1fa89 README: explain how to do out-of-tree builds. 2020-04-24 23:27:43 +00:00
whitequark 2106f78bb1 ast/simplify: improve enum handling.
Before this commit, enum values were serialized as attributes of form
  \enum_<width>_<value>
where <value> was a decimal signed integer.

This has multiple drawbacks:
  * Enums with large values would be hard to process for downstream
    tooling that cannot parse arbitrary precision decimals. (In fact
    Yosys also did not correctly process enums with large values,
    and would overflow `int`.)
  * Enum value attributes were not confined to their own namespace,
    making it harder for downstream tooling to enumerate all such
    attributes, as opposed to looking up any specific value.
  * Enum values could not include x or z, which are explicitly
    permitted in the SystemVerilog standard.

After this commit, enum values are serialized as attributes of form
  \enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
Peter Crozier ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Claire Wolf ed4fa19ba2 Update Copyright
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-16 16:28:25 +01:00
Waldir Pimenta 418c069561 License: bump year and add title 2020-03-14 16:46:07 +00:00
Eddie Hung 0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00