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Add multidimensional arrays to SystemVerilog features in README
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@ -587,7 +587,13 @@ from SystemVerilog:
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- enums are supported (including inside packages)
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- but are currently not strongly typed
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- packed structs and unions are supported.
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- packed structs and unions are supported
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- arrays of packed structs/unions are currently not supported
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- structure literals are currently not supported
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- multidimensional arrays are supported
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- array assignment of unpacked arrays is currently not supported
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- array literals are currently not supported
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- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
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ports are inputs or outputs are supported.
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