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/*
* yosys - - Yosys Open SYnthesis Suite
*
* Copyright ( C ) 2014 Clifford Wolf < clifford @ clifford . at >
* Copyright ( C ) 2014 Johann Glaser < Johann . Glaser @ gmx . at >
*
* Permission to use , copy , modify , and / or distribute this software for any
* purpose with or without fee is hereby granted , provided that the above
* copyright notice and this permission notice appear in all copies .
*
* THE SOFTWARE IS PROVIDED " AS IS " AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS . IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL , DIRECT , INDIRECT , OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE , DATA OR PROFITS , WHETHER IN AN
* ACTION OF CONTRACT , NEGLIGENCE OR OTHER TORTIOUS ACTION , ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE .
*
*/
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# include "kernel/yosys.h"
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# include "kernel/satgen.h"
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# include "kernel/consteval.h"
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# include "kernel/celledges.h"
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# include "kernel/macc.h"
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# include <algorithm>
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USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
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static uint32_t xorshift32_state = 123456789 ;
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static uint32_t xorshift32 ( uint32_t limit ) {
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xorshift32_state ^ = xorshift32_state < < 13 ;
xorshift32_state ^ = xorshift32_state > > 17 ;
xorshift32_state ^ = xorshift32_state < < 5 ;
return xorshift32_state % limit ;
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}
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static void create_gold_module ( RTLIL : : Design * design , RTLIL : : IdString cell_type , std : : string cell_type_flags , bool constmode , bool muxdiv )
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{
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RTLIL : : Module * module = design - > addModule ( ID ( gold ) ) ;
RTLIL : : Cell * cell = module - > addCell ( ID ( UUT ) , cell_type ) ;
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RTLIL : : Wire * wire ;
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if ( cell_type . in ( ID ( $ mux ) , ID ( $ pmux ) ) )
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{
int width = 1 + xorshift32 ( 8 ) ;
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int swidth = cell_type = = ID ( $ mux ) ? 1 : 1 + xorshift32 ( 8 ) ;
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wire = module - > addWire ( ID : : A ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : A , wire ) ;
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wire = module - > addWire ( ID : : B ) ;
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wire - > width = width * swidth ;
wire - > port_input = true ;
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cell - > setPort ( ID : : B , wire ) ;
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wire = module - > addWire ( ID : : S ) ;
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wire - > width = swidth ;
wire - > port_input = true ;
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cell - > setPort ( ID : : S , wire ) ;
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wire = module - > addWire ( ID : : Y ) ;
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wire - > width = width ;
wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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}
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if ( cell_type = = ID ( $ fa ) )
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{
int width = 1 + xorshift32 ( 8 ) ;
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wire = module - > addWire ( ID : : A ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : A , wire ) ;
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wire = module - > addWire ( ID : : B ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : B , wire ) ;
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wire = module - > addWire ( ID : : C ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : C , wire ) ;
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wire = module - > addWire ( ID : : X ) ;
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wire - > width = width ;
wire - > port_output = true ;
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cell - > setPort ( ID : : X , wire ) ;
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wire = module - > addWire ( ID : : Y ) ;
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wire - > width = width ;
wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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}
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if ( cell_type = = ID ( $ lcu ) )
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{
int width = 1 + xorshift32 ( 8 ) ;
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wire = module - > addWire ( ID : : P ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : P , wire ) ;
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wire = module - > addWire ( ID : : G ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : G , wire ) ;
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wire = module - > addWire ( ID : : CI ) ;
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wire - > port_input = true ;
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cell - > setPort ( ID : : CI , wire ) ;
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wire = module - > addWire ( ID : : CO ) ;
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wire - > width = width ;
wire - > port_output = true ;
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cell - > setPort ( ID : : CO , wire ) ;
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}
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if ( cell_type = = ID ( $ macc ) )
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{
Macc macc ;
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int width = 1 + xorshift32 ( 8 ) ;
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int depth = 1 + xorshift32 ( 6 ) ;
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int mulbits_a = 0 , mulbits_b = 0 ;
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RTLIL : : Wire * wire_a = module - > addWire ( ID : : A ) ;
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wire_a - > width = 0 ;
wire_a - > port_input = true ;
for ( int i = 0 ; i < depth ; i + + )
{
int size_a = xorshift32 ( width ) + 1 ;
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int size_b = depth > 4 ? 0 : xorshift32 ( width ) + 1 ;
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if ( mulbits_a + size_a * size_b < = 96 & & mulbits_b + size_a + size_b < = 16 & & xorshift32 ( 2 ) = = 1 ) {
mulbits_a + = size_a * size_b ;
mulbits_b + = size_a + size_b ;
} else
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size_b = 0 ;
Macc : : port_t this_port ;
wire_a - > width + = size_a ;
this_port . in_a = RTLIL : : SigSpec ( wire_a , wire_a - > width - size_a , size_a ) ;
wire_a - > width + = size_b ;
this_port . in_b = RTLIL : : SigSpec ( wire_a , wire_a - > width - size_b , size_b ) ;
this_port . is_signed = xorshift32 ( 2 ) = = 1 ;
this_port . do_subtract = xorshift32 ( 2 ) = = 1 ;
macc . ports . push_back ( this_port ) ;
}
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wire = module - > addWire ( ID : : B ) ;
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wire - > width = xorshift32 ( mulbits_a ? xorshift32 ( 4 ) + 1 : xorshift32 ( 16 ) + 1 ) ;
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wire - > port_input = true ;
macc . bit_ports = wire ;
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wire = module - > addWire ( ID : : Y ) ;
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wire - > width = width ;
wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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macc . to_cell ( cell ) ;
}
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if ( cell_type = = ID ( $ lut ) )
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{
int width = 1 + xorshift32 ( 6 ) ;
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wire = module - > addWire ( ID : : A ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : A , wire ) ;
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wire = module - > addWire ( ID : : Y ) ;
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wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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RTLIL : : SigSpec config ;
for ( int i = 0 ; i < ( 1 < < width ) ; i + + )
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config . append ( xorshift32 ( 2 ) ? State : : S1 : State : : S0 ) ;
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cell - > setParam ( ID : : LUT , config . as_const ( ) ) ;
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}
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if ( cell_type = = ID ( $ sop ) )
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{
int width = 1 + xorshift32 ( 8 ) ;
int depth = 1 + xorshift32 ( 8 ) ;
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wire = module - > addWire ( ID : : A ) ;
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wire - > width = width ;
wire - > port_input = true ;
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cell - > setPort ( ID : : A , wire ) ;
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wire = module - > addWire ( ID : : Y ) ;
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wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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RTLIL : : SigSpec config ;
for ( int i = 0 ; i < width * depth ; i + + )
switch ( xorshift32 ( 3 ) ) {
case 0 :
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config . append ( State : : S1 ) ;
config . append ( State : : S0 ) ;
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break ;
case 1 :
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config . append ( State : : S0 ) ;
config . append ( State : : S1 ) ;
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break ;
case 2 :
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config . append ( State : : S0 ) ;
config . append ( State : : S0 ) ;
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break ;
}
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cell - > setParam ( ID : : DEPTH , depth ) ;
cell - > setParam ( ID : : TABLE , config . as_const ( ) ) ;
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}
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if ( cell_type_flags . find ( ' A ' ) ! = std : : string : : npos ) {
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wire = module - > addWire ( ID : : A ) ;
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wire - > width = 1 + xorshift32 ( 8 ) ;
wire - > port_input = true ;
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cell - > setPort ( ID : : A , wire ) ;
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}
if ( cell_type_flags . find ( ' B ' ) ! = std : : string : : npos ) {
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wire = module - > addWire ( ID : : B ) ;
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if ( cell_type_flags . find ( ' h ' ) ! = std : : string : : npos )
wire - > width = 1 + xorshift32 ( 6 ) ;
else
wire - > width = 1 + xorshift32 ( 8 ) ;
wire - > port_input = true ;
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cell - > setPort ( ID : : B , wire ) ;
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}
if ( cell_type_flags . find ( ' S ' ) ! = std : : string : : npos & & xorshift32 ( 2 ) ) {
if ( cell_type_flags . find ( ' A ' ) ! = std : : string : : npos )
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cell - > parameters [ ID : : A_SIGNED ] = true ;
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if ( cell_type_flags . find ( ' B ' ) ! = std : : string : : npos )
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cell - > parameters [ ID : : B_SIGNED ] = true ;
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}
if ( cell_type_flags . find ( ' s ' ) ! = std : : string : : npos ) {
if ( cell_type_flags . find ( ' A ' ) ! = std : : string : : npos & & xorshift32 ( 2 ) )
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cell - > parameters [ ID : : A_SIGNED ] = true ;
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if ( cell_type_flags . find ( ' B ' ) ! = std : : string : : npos & & xorshift32 ( 2 ) )
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cell - > parameters [ ID : : B_SIGNED ] = true ;
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}
if ( cell_type_flags . find ( ' Y ' ) ! = std : : string : : npos ) {
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wire = module - > addWire ( ID : : Y ) ;
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wire - > width = 1 + xorshift32 ( 8 ) ;
wire - > port_output = true ;
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cell - > setPort ( ID : : Y , wire ) ;
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}
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if ( muxdiv & & cell_type . in ( ID ( $ div ) , ID ( $ mod ) , ID ( $ divfloor ) , ID ( $ modfloor ) ) ) {
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auto b_not_zero = module - > ReduceBool ( NEW_ID , cell - > getPort ( ID : : B ) ) ;
auto div_out = module - > addWire ( NEW_ID , GetSize ( cell - > getPort ( ID : : Y ) ) ) ;
module - > addMux ( NEW_ID , RTLIL : : SigSpec ( 0 , GetSize ( div_out ) ) , div_out , b_not_zero , cell - > getPort ( ID : : Y ) ) ;
cell - > setPort ( ID : : Y , div_out ) ;
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}
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if ( cell_type = = ID ( $ alu ) )
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{
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wire = module - > addWire ( ID : : CI ) ;
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wire - > port_input = true ;
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cell - > setPort ( ID : : CI , wire ) ;
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wire = module - > addWire ( ID : : BI ) ;
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wire - > port_input = true ;
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cell - > setPort ( ID : : BI , wire ) ;
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wire = module - > addWire ( ID : : X ) ;
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wire - > width = GetSize ( cell - > getPort ( ID : : Y ) ) ;
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wire - > port_output = true ;
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cell - > setPort ( ID : : X , wire ) ;
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wire = module - > addWire ( ID : : CO ) ;
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wire - > width = GetSize ( cell - > getPort ( ID : : Y ) ) ;
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wire - > port_output = true ;
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cell - > setPort ( ID : : CO , wire ) ;
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}
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if ( constmode )
{
auto conn_list = cell - > connections ( ) ;
for ( auto & conn : conn_list )
{
RTLIL : : SigSpec sig = conn . second ;
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if ( GetSize ( sig ) = = 0 | | sig [ 0 ] . wire = = nullptr | | sig [ 0 ] . wire - > port_output )
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continue ;
int n , m ;
switch ( xorshift32 ( 5 ) )
{
case 0 :
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n = xorshift32 ( GetSize ( sig ) + 1 ) ;
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for ( int i = 0 ; i < n ; i + + )
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sig [ i ] = xorshift32 ( 2 ) = = 1 ? State : : S1 : State : : S0 ;
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break ;
case 1 :
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n = xorshift32 ( GetSize ( sig ) + 1 ) ;
for ( int i = n ; i < GetSize ( sig ) ; i + + )
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sig [ i ] = xorshift32 ( 2 ) = = 1 ? State : : S1 : State : : S0 ;
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break ;
case 2 :
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n = xorshift32 ( GetSize ( sig ) ) ;
m = xorshift32 ( GetSize ( sig ) ) ;
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for ( int i = min ( n , m ) ; i < max ( n , m ) ; i + + )
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sig [ i ] = xorshift32 ( 2 ) = = 1 ? State : : S1 : State : : S0 ;
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break ;
}
cell - > setPort ( conn . first , sig ) ;
}
}
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module - > fixup_ports ( ) ;
cell - > fixup_parameters ( ) ;
cell - > check ( ) ;
}
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static void run_edges_test ( RTLIL : : Design * design , bool verbose )
{
Module * module = * design - > modules ( ) . begin ( ) ;
Cell * cell = * module - > cells ( ) . begin ( ) ;
ezSatPtr ezptr ;
ezSAT & ez = * ezptr . get ( ) ;
SigMap sigmap ( module ) ;
SatGen satgen ( & ez , & sigmap ) ;
FwdCellEdgesDatabase edges_db ( sigmap ) ;
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if ( ! edges_db . add_edges_from_cell ( cell ) )
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log_error ( " Creating edge database failed for this cell! \n " ) ;
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dict < SigBit , pool < SigBit > > satgen_db ;
satgen . setContext ( & sigmap , " X: " ) ;
satgen . importCell ( cell ) ;
satgen . setContext ( & sigmap , " Y: " ) ;
satgen . importCell ( cell ) ;
vector < tuple < SigBit , int , int > > input_db , output_db ;
for ( auto & conn : cell - > connections ( ) )
{
SigSpec bits = sigmap ( conn . second ) ;
satgen . setContext ( & sigmap , " X: " ) ;
std : : vector < int > xbits = satgen . importSigSpec ( bits ) ;
satgen . setContext ( & sigmap , " Y: " ) ;
std : : vector < int > ybits = satgen . importSigSpec ( bits ) ;
for ( int i = 0 ; i < GetSize ( bits ) ; i + + )
if ( cell - > input ( conn . first ) )
input_db . emplace_back ( bits [ i ] , xbits [ i ] , ybits [ i ] ) ;
else
output_db . emplace_back ( bits [ i ] , xbits [ i ] , ybits [ i ] ) ;
}
if ( verbose )
log ( " \n SAT solving for all edges: \n " ) ;
for ( int i = 0 ; i < GetSize ( input_db ) ; i + + )
{
SigBit inbit = std : : get < 0 > ( input_db [ i ] ) ;
if ( verbose )
log ( " Testing input signal %s: \n " , log_signal ( inbit ) ) ;
vector < int > xinbits , yinbits ;
for ( int k = 0 ; k < GetSize ( input_db ) ; k + + )
if ( k ! = i ) {
xinbits . push_back ( std : : get < 1 > ( input_db [ k ] ) ) ;
yinbits . push_back ( std : : get < 2 > ( input_db [ k ] ) ) ;
}
int xyinbit_ok = ez . vec_eq ( xinbits , yinbits ) ;
for ( int k = 0 ; k < GetSize ( output_db ) ; k + + )
{
SigBit outbit = std : : get < 0 > ( output_db [ k ] ) ;
int xoutbit = std : : get < 1 > ( output_db [ k ] ) ;
int youtbit = std : : get < 2 > ( output_db [ k ] ) ;
bool is_edge = ez . solve ( xyinbit_ok , ez . XOR ( xoutbit , youtbit ) ) ;
if ( is_edge )
satgen_db [ inbit ] . insert ( outbit ) ;
if ( verbose ) {
bool is_ref_edge = edges_db . db . count ( inbit ) & & edges_db . db . at ( inbit ) . count ( outbit ) ;
log ( " %c %s %s \n " , is_edge ? ' x ' : ' o ' , log_signal ( outbit ) , is_edge = = is_ref_edge ? " OK " : " ERROR " ) ;
}
}
}
if ( satgen_db = = edges_db . db )
log ( " PASS. \n " ) ;
else
log_error ( " SAT-based edge table does not match the database! \n " ) ;
}
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static void run_eval_test ( RTLIL : : Design * design , bool verbose , bool nosat , std : : string uut_name , std : : ofstream & vlog_file )
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{
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log ( " Eval testing:%c " , verbose ? ' \n ' : ' ' ) ;
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RTLIL : : Module * gold_mod = design - > module ( ID ( gold ) ) ;
RTLIL : : Module * gate_mod = design - > module ( ID ( gate ) ) ;
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ConstEval gold_ce ( gold_mod ) , gate_ce ( gate_mod ) ;
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ezSatPtr ez1 , ez2 ;
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SigMap sigmap ( gold_mod ) ;
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SatGen satgen1 ( ez1 . get ( ) , & sigmap ) ;
SatGen satgen2 ( ez2 . get ( ) , & sigmap ) ;
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satgen2 . model_undef = true ;
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if ( ! nosat )
for ( auto cell : gold_mod - > cells ( ) ) {
satgen1 . importCell ( cell ) ;
satgen2 . importCell ( cell ) ;
}
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if ( vlog_file . is_open ( ) )
{
vlog_file < < stringf ( " \n module %s; \n " , uut_name . c_str ( ) ) ;
for ( auto port : gold_mod - > ports ) {
RTLIL : : Wire * wire = gold_mod - > wire ( port ) ;
if ( wire - > port_input )
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vlog_file < < stringf ( " reg [%d:0] %s; \n " , GetSize ( wire ) - 1 , log_id ( wire ) ) ;
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else
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vlog_file < < stringf ( " wire [%d:0] %s_expr, %s_noexpr; \n " , GetSize ( wire ) - 1 , log_id ( wire ) , log_id ( wire ) ) ;
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}
vlog_file < < stringf ( " %s_expr uut_expr( " , uut_name . c_str ( ) ) ;
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for ( int i = 0 ; i < GetSize ( gold_mod - > ports ) ; i + + )
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vlog_file < < stringf ( " %s.%s(%s%s) " , i ? " , " : " " , log_id ( gold_mod - > ports [ i ] ) , log_id ( gold_mod - > ports [ i ] ) ,
gold_mod - > wire ( gold_mod - > ports [ i ] ) - > port_input ? " " : " _expr " ) ;
vlog_file < < stringf ( " ); \n " ) ;
vlog_file < < stringf ( " %s_expr uut_noexpr( " , uut_name . c_str ( ) ) ;
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for ( int i = 0 ; i < GetSize ( gold_mod - > ports ) ; i + + )
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vlog_file < < stringf ( " %s.%s(%s%s) " , i ? " , " : " " , log_id ( gold_mod - > ports [ i ] ) , log_id ( gold_mod - > ports [ i ] ) ,
gold_mod - > wire ( gold_mod - > ports [ i ] ) - > port_input ? " " : " _noexpr " ) ;
vlog_file < < stringf ( " ); \n " ) ;
vlog_file < < stringf ( " task run; \n " ) ;
vlog_file < < stringf ( " begin \n " ) ;
vlog_file < < stringf ( " $display( \" %s \" ); \n " , uut_name . c_str ( ) ) ;
}
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for ( int i = 0 ; i < 64 ; i + + )
{
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log ( verbose ? " \n " : " . " ) ;
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gold_ce . clear ( ) ;
gate_ce . clear ( ) ;
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RTLIL : : SigSpec in_sig , in_val ;
RTLIL : : SigSpec out_sig , out_val ;
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std : : string vlog_pattern_info ;
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for ( auto port : gold_mod - > ports )
{
RTLIL : : Wire * gold_wire = gold_mod - > wire ( port ) ;
RTLIL : : Wire * gate_wire = gate_mod - > wire ( port ) ;
log_assert ( gold_wire ! = nullptr ) ;
log_assert ( gate_wire ! = nullptr ) ;
log_assert ( gold_wire - > port_input = = gate_wire - > port_input ) ;
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log_assert ( GetSize ( gold_wire ) = = GetSize ( gate_wire ) ) ;
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if ( ! gold_wire - > port_input )
continue ;
RTLIL : : Const in_value ;
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for ( int i = 0 ; i < GetSize ( gold_wire ) ; i + + )
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in_value . bits . push_back ( xorshift32 ( 2 ) ? State : : S1 : State : : S0 ) ;
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if ( xorshift32 ( 4 ) = = 0 ) {
int inv_chance = 1 + xorshift32 ( 8 ) ;
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for ( int i = 0 ; i < GetSize ( gold_wire ) ; i + + )
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if ( xorshift32 ( inv_chance ) = = 0 )
in_value . bits [ i ] = RTLIL : : Sx ;
}
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if ( verbose )
log ( " %s: %s \n " , log_id ( gold_wire ) , log_signal ( in_value ) ) ;
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in_sig . append ( gold_wire ) ;
in_val . append ( in_value ) ;
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gold_ce . set ( gold_wire , in_value ) ;
gate_ce . set ( gate_wire , in_value ) ;
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if ( vlog_file . is_open ( ) & & GetSize ( in_value ) > 0 ) {
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vlog_file < < stringf ( " %s = 'b%s; \n " , log_id ( gold_wire ) , in_value . as_string ( ) . c_str ( ) ) ;
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if ( ! vlog_pattern_info . empty ( ) )
vlog_pattern_info + = " " ;
vlog_pattern_info + = stringf ( " %s=%s " , log_id ( gold_wire ) , log_signal ( in_value ) ) ;
}
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}
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if ( vlog_file . is_open ( ) )
vlog_file < < stringf ( " #1; \n " ) ;
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for ( auto port : gold_mod - > ports )
{
RTLIL : : Wire * gold_wire = gold_mod - > wire ( port ) ;
RTLIL : : Wire * gate_wire = gate_mod - > wire ( port ) ;
log_assert ( gold_wire ! = nullptr ) ;
log_assert ( gate_wire ! = nullptr ) ;
log_assert ( gold_wire - > port_output = = gate_wire - > port_output ) ;
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log_assert ( GetSize ( gold_wire ) = = GetSize ( gate_wire ) ) ;
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if ( ! gold_wire - > port_output )
continue ;
RTLIL : : SigSpec gold_outval ( gold_wire ) ;
RTLIL : : SigSpec gate_outval ( gate_wire ) ;
if ( ! gold_ce . eval ( gold_outval ) )
log_error ( " Failed to eval %s in gold module. \n " , log_id ( gold_wire ) ) ;
if ( ! gate_ce . eval ( gate_outval ) )
log_error ( " Failed to eval %s in gate module. \n " , log_id ( gate_wire ) ) ;
bool gold_gate_mismatch = false ;
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for ( int i = 0 ; i < GetSize ( gold_wire ) ; i + + ) {
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if ( gold_outval [ i ] = = RTLIL : : Sx )
continue ;
if ( gold_outval [ i ] = = gate_outval [ i ] )
continue ;
gold_gate_mismatch = true ;
break ;
}
if ( gold_gate_mismatch )
log_error ( " Mismatch in output %s: gold:%s != gate:%s \n " , log_id ( gate_wire ) , log_signal ( gold_outval ) , log_signal ( gate_outval ) ) ;
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if ( verbose )
log ( " %s: %s \n " , log_id ( gold_wire ) , log_signal ( gold_outval ) ) ;
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out_sig . append ( gold_wire ) ;
out_val . append ( gold_outval ) ;
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if ( vlog_file . is_open ( ) ) {
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vlog_file < < stringf ( " $display( \" [%s] %s expected: %%b, expr: %%b, noexpr: %%b \" , %d'b%s, %s_expr, %s_noexpr); \n " ,
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vlog_pattern_info . c_str ( ) , log_id ( gold_wire ) , GetSize ( gold_outval ) , gold_outval . as_string ( ) . c_str ( ) , log_id ( gold_wire ) , log_id ( gold_wire ) ) ;
vlog_file < < stringf ( " if (%s_expr !== %d'b%s) begin $display( \" ERROR \" ); $finish; end \n " , log_id ( gold_wire ) , GetSize ( gold_outval ) , gold_outval . as_string ( ) . c_str ( ) ) ;
vlog_file < < stringf ( " if (%s_noexpr !== %d'b%s) begin $display( \" ERROR \" ); $finish; end \n " , log_id ( gold_wire ) , GetSize ( gold_outval ) , gold_outval . as_string ( ) . c_str ( ) ) ;
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}
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}
if ( verbose )
log ( " EVAL: %s \n " , out_val . as_string ( ) . c_str ( ) ) ;
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if ( ! nosat )
{
std : : vector < int > sat1_in_sig = satgen1 . importSigSpec ( in_sig ) ;
std : : vector < int > sat1_in_val = satgen1 . importSigSpec ( in_val ) ;
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std : : vector < int > sat1_model = satgen1 . importSigSpec ( out_sig ) ;
std : : vector < bool > sat1_model_value ;
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if ( ! ez1 - > solve ( sat1_model , sat1_model_value , ez1 - > vec_eq ( sat1_in_sig , sat1_in_val ) ) )
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log_error ( " Evaluating sat model 1 (no undef modeling) failed! \n " ) ;
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if ( verbose ) {
log ( " SAT 1: " ) ;
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for ( int i = GetSize ( out_sig ) - 1 ; i > = 0 ; i - - )
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log ( " %c " , sat1_model_value . at ( i ) ? ' 1 ' : ' 0 ' ) ;
log ( " \n " ) ;
}
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for ( int i = 0 ; i < GetSize ( out_sig ) ; i + + ) {
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if ( out_val [ i ] ! = State : : S0 & & out_val [ i ] ! = State : : S1 )
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continue ;
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if ( out_val [ i ] = = State : : S0 & & sat1_model_value . at ( i ) = = false )
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continue ;
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if ( out_val [ i ] = = State : : S1 & & sat1_model_value . at ( i ) = = true )
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continue ;
log_error ( " Mismatch in sat model 1 (no undef modeling) output! \n " ) ;
}
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std : : vector < int > sat2_in_def_sig = satgen2 . importDefSigSpec ( in_sig ) ;
std : : vector < int > sat2_in_def_val = satgen2 . importDefSigSpec ( in_val ) ;
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std : : vector < int > sat2_in_undef_sig = satgen2 . importUndefSigSpec ( in_sig ) ;
std : : vector < int > sat2_in_undef_val = satgen2 . importUndefSigSpec ( in_val ) ;
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std : : vector < int > sat2_model_def_sig = satgen2 . importDefSigSpec ( out_sig ) ;
std : : vector < int > sat2_model_undef_sig = satgen2 . importUndefSigSpec ( out_sig ) ;
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std : : vector < int > sat2_model ;
sat2_model . insert ( sat2_model . end ( ) , sat2_model_def_sig . begin ( ) , sat2_model_def_sig . end ( ) ) ;
sat2_model . insert ( sat2_model . end ( ) , sat2_model_undef_sig . begin ( ) , sat2_model_undef_sig . end ( ) ) ;
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std : : vector < bool > sat2_model_value ;
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if ( ! ez2 - > solve ( sat2_model , sat2_model_value , ez2 - > vec_eq ( sat2_in_def_sig , sat2_in_def_val ) , ez2 - > vec_eq ( sat2_in_undef_sig , sat2_in_undef_val ) ) )
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log_error ( " Evaluating sat model 2 (undef modeling) failed! \n " ) ;
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if ( verbose ) {
log ( " SAT 2: " ) ;
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for ( int i = GetSize ( out_sig ) - 1 ; i > = 0 ; i - - )
log ( " %c " , sat2_model_value . at ( GetSize ( out_sig ) + i ) ? ' x ' : sat2_model_value . at ( i ) ? ' 1 ' : ' 0 ' ) ;
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log ( " \n " ) ;
}
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for ( int i = 0 ; i < GetSize ( out_sig ) ; i + + ) {
if ( sat2_model_value . at ( GetSize ( out_sig ) + i ) ) {
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if ( out_val [ i ] ! = State : : S0 & & out_val [ i ] ! = State : : S1 )
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continue ;
} else {
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if ( out_val [ i ] = = State : : S0 & & sat2_model_value . at ( i ) = = false )
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continue ;
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if ( out_val [ i ] = = State : : S1 & & sat2_model_value . at ( i ) = = true )
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continue ;
}
log_error ( " Mismatch in sat model 2 (undef modeling) output! \n " ) ;
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}
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}
}
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if ( vlog_file . is_open ( ) ) {
vlog_file < < stringf ( " end \n " ) ;
vlog_file < < stringf ( " endtask \n " ) ;
vlog_file < < stringf ( " endmodule \n " ) ;
}
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if ( ! verbose )
log ( " ok. \n " ) ;
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}
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struct TestCellPass : public Pass {
TestCellPass ( ) : Pass ( " test_cell " , " automatically test the implementation of a cell type " ) { }
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void help ( ) override
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{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log ( " \n " ) ;
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log ( " test_cell [options] {cell-types} \n " ) ;
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log ( " \n " ) ;
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log ( " Tests the internal implementation of the given cell type (for example '$add') \n " ) ;
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log ( " by comparing SAT solver, EVAL and TECHMAP implementations of the cell types.. \n " ) ;
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log ( " \n " ) ;
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log ( " Run with 'all' instead of a cell type to run the test on all supported \n " ) ;
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log ( " cell types. Use for example 'all /$add' for all cell types except $add. \n " ) ;
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log ( " \n " ) ;
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log ( " -n {integer} \n " ) ;
log ( " create this number of cell instances and test them (default = 100). \n " ) ;
log ( " \n " ) ;
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log ( " -s {positive_integer} \n " ) ;
log ( " use this value as rng seed value (default = unix time). \n " ) ;
log ( " \n " ) ;
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log ( " -f {ilang_file} \n " ) ;
log ( " don't generate circuits. instead load the specified ilang file. \n " ) ;
log ( " \n " ) ;
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log ( " -w {filename_prefix} \n " ) ;
log ( " don't test anything. just generate the circuits and write them \n " ) ;
log ( " to ilang files with the specified prefix \n " ) ;
log ( " \n " ) ;
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log ( " -map {filename} \n " ) ;
log ( " pass this option to techmap. \n " ) ;
log ( " \n " ) ;
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log ( " -simlib \n " ) ;
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log ( " use \" techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc \" \n " ) ;
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log ( " \n " ) ;
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log ( " -aigmap \n " ) ;
log ( " instead of calling \" techmap \" , call \" aigmap \" \n " ) ;
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log ( " \n " ) ;
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log ( " -muxdiv \n " ) ;
log ( " when creating test benches with dividers, create an additional mux \n " ) ;
log ( " to mask out the division-by-zero case \n " ) ;
log ( " \n " ) ;
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log ( " -script {script_file} \n " ) ;
log ( " instead of calling \" techmap \" , call \" script {script_file} \" . \n " ) ;
log ( " \n " ) ;
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log ( " -const \n " ) ;
log ( " set some input bits to random constant values \n " ) ;
log ( " \n " ) ;
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log ( " -nosat \n " ) ;
log ( " do not check SAT model or run SAT equivalence checking \n " ) ;
log ( " \n " ) ;
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log ( " -noeval \n " ) ;
log ( " do not check const-eval models \n " ) ;
log ( " \n " ) ;
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log ( " -edges \n " ) ;
log ( " test cell edges db creator against sat-based implementation \n " ) ;
log ( " \n " ) ;
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log ( " -v \n " ) ;
log ( " print additional debug information to the console \n " ) ;
log ( " \n " ) ;
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log ( " -vlog {filename} \n " ) ;
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log ( " create a Verilog test bench to test simlib and write_verilog \n " ) ;
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log ( " \n " ) ;
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}
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void execute ( std : : vector < std : : string > args , RTLIL : : Design * ) override
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{
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int num_iter = 100 ;
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std : : string techmap_cmd = " techmap -assert " ;
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std : : string ilang_file , write_prefix ;
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xorshift32_state = 0 ;
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std : : ofstream vlog_file ;
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bool muxdiv = false ;
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bool verbose = false ;
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bool constmode = false ;
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bool nosat = false ;
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bool noeval = false ;
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bool edges = false ;
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int argidx ;
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for ( argidx = 1 ; argidx < GetSize ( args ) ; argidx + + )
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{
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if ( args [ argidx ] = = " -n " & & argidx + 1 < GetSize ( args ) ) {
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num_iter = atoi ( args [ + + argidx ] . c_str ( ) ) ;
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continue ;
}
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if ( args [ argidx ] = = " -s " & & argidx + 1 < GetSize ( args ) ) {
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xorshift32_state = atoi ( args [ + + argidx ] . c_str ( ) ) ;
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continue ;
}
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if ( args [ argidx ] = = " -map " & & argidx + 1 < GetSize ( args ) ) {
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techmap_cmd + = " -map " + args [ + + argidx ] ;
continue ;
}
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if ( args [ argidx ] = = " -f " & & argidx + 1 < GetSize ( args ) ) {
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ilang_file = args [ + + argidx ] ;
num_iter = 1 ;
continue ;
}
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if ( args [ argidx ] = = " -w " & & argidx + 1 < GetSize ( args ) ) {
write_prefix = args [ + + argidx ] ;
continue ;
}
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if ( args [ argidx ] = = " -script " & & argidx + 1 < GetSize ( args ) ) {
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techmap_cmd = " script " + args [ + + argidx ] ;
continue ;
}
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if ( args [ argidx ] = = " -simlib " ) {
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techmap_cmd = " techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc " ;
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continue ;
}
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if ( args [ argidx ] = = " -aigmap " ) {
techmap_cmd = " aigmap " ;
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continue ;
}
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if ( args [ argidx ] = = " -muxdiv " ) {
muxdiv = true ;
continue ;
}
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if ( args [ argidx ] = = " -const " ) {
constmode = true ;
continue ;
}
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if ( args [ argidx ] = = " -nosat " ) {
nosat = true ;
continue ;
}
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if ( args [ argidx ] = = " -noeval " ) {
noeval = true ;
continue ;
}
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if ( args [ argidx ] = = " -edges " ) {
edges = true ;
continue ;
}
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if ( args [ argidx ] = = " -v " ) {
verbose = true ;
continue ;
}
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if ( args [ argidx ] = = " -vlog " & & argidx + 1 < GetSize ( args ) ) {
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vlog_file . open ( args [ + + argidx ] , std : : ios_base : : trunc ) ;
if ( ! vlog_file . is_open ( ) )
log_cmd_error ( " Failed to open output file `%s'. \n " , args [ argidx ] . c_str ( ) ) ;
continue ;
}
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break ;
}
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if ( xorshift32_state = = 0 ) {
xorshift32_state = time ( NULL ) & 0x7fffffff ;
log ( " Rng seed value: %d \n " , int ( xorshift32_state ) ) ;
}
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std : : map < IdString , std : : string > cell_types ;
std : : vector < IdString > selected_cell_types ;
cell_types [ ID ( $ not ) ] = " ASY " ;
cell_types [ ID ( $ pos ) ] = " ASY " ;
cell_types [ ID ( $ neg ) ] = " ASY " ;
cell_types [ ID ( $ and ) ] = " ABSY " ;
cell_types [ ID ( $ or ) ] = " ABSY " ;
cell_types [ ID ( $ xor ) ] = " ABSY " ;
cell_types [ ID ( $ xnor ) ] = " ABSY " ;
cell_types [ ID ( $ reduce_and ) ] = " ASY " ;
cell_types [ ID ( $ reduce_or ) ] = " ASY " ;
cell_types [ ID ( $ reduce_xor ) ] = " ASY " ;
cell_types [ ID ( $ reduce_xnor ) ] = " ASY " ;
cell_types [ ID ( $ reduce_bool ) ] = " ASY " ;
cell_types [ ID ( $ shl ) ] = " ABshY " ;
cell_types [ ID ( $ shr ) ] = " ABshY " ;
cell_types [ ID ( $ sshl ) ] = " ABshY " ;
cell_types [ ID ( $ sshr ) ] = " ABshY " ;
cell_types [ ID ( $ shift ) ] = " ABshY " ;
cell_types [ ID ( $ shiftx ) ] = " ABshY " ;
cell_types [ ID ( $ lt ) ] = " ABSY " ;
cell_types [ ID ( $ le ) ] = " ABSY " ;
cell_types [ ID ( $ eq ) ] = " ABSY " ;
cell_types [ ID ( $ ne ) ] = " ABSY " ;
// cell_types[ID($eqx)] = "ABSY";
// cell_types[ID($nex)] = "ABSY";
cell_types [ ID ( $ ge ) ] = " ABSY " ;
cell_types [ ID ( $ gt ) ] = " ABSY " ;
cell_types [ ID ( $ add ) ] = " ABSY " ;
cell_types [ ID ( $ sub ) ] = " ABSY " ;
cell_types [ ID ( $ mul ) ] = " ABSY " ;
cell_types [ ID ( $ div ) ] = " ABSY " ;
cell_types [ ID ( $ mod ) ] = " ABSY " ;
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cell_types [ ID ( $ divfloor ) ] = " ABSY " ;
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cell_types [ ID ( $ modfloor ) ] = " ABSY " ;
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// cell_types[ID($pow)] = "ABsY";
cell_types [ ID ( $ logic_not ) ] = " ASY " ;
cell_types [ ID ( $ logic_and ) ] = " ABSY " ;
cell_types [ ID ( $ logic_or ) ] = " ABSY " ;
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if ( edges ) {
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cell_types [ ID ( $ mux ) ] = " * " ;
cell_types [ ID ( $ pmux ) ] = " * " ;
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}
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// cell_types[ID($slice)] = "A";
// cell_types[ID($concat)] = "A";
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cell_types [ ID ( $ lut ) ] = " * " ;
cell_types [ ID ( $ sop ) ] = " * " ;
cell_types [ ID ( $ alu ) ] = " ABSY " ;
cell_types [ ID ( $ lcu ) ] = " * " ;
cell_types [ ID ( $ macc ) ] = " * " ;
cell_types [ ID ( $ fa ) ] = " * " ;
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for ( ; argidx < GetSize ( args ) ; argidx + + )
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{
if ( args [ argidx ] . rfind ( " - " , 0 ) = = 0 )
log_cmd_error ( " Unexpected option: %s \n " , args [ argidx ] . c_str ( ) ) ;
if ( args [ argidx ] = = " all " ) {
for ( auto & it : cell_types )
if ( std : : count ( selected_cell_types . begin ( ) , selected_cell_types . end ( ) , it . first ) = = 0 )
selected_cell_types . push_back ( it . first ) ;
continue ;
}
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if ( args [ argidx ] . compare ( 0 , 1 , " / " ) = = 0 ) {
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std : : vector < IdString > new_selected_cell_types ;
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for ( auto it : selected_cell_types )
if ( it ! = args [ argidx ] . substr ( 1 ) )
new_selected_cell_types . push_back ( it ) ;
new_selected_cell_types . swap ( selected_cell_types ) ;
continue ;
}
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if ( cell_types . count ( args [ argidx ] ) = = 0 ) {
std : : string cell_type_list ;
int charcount = 100 ;
for ( auto & it : cell_types ) {
if ( charcount > 60 ) {
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cell_type_list + = stringf ( " \n %s " , + log_id ( it . first ) ) ;
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charcount = 0 ;
} else
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cell_type_list + = stringf ( " %s " , log_id ( it . first ) ) ;
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charcount + = GetSize ( it . first ) ;
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}
log_cmd_error ( " The cell type `%s' is currently not supported. Try one of these:%s \n " ,
args [ argidx ] . c_str ( ) , cell_type_list . c_str ( ) ) ;
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}
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if ( std : : count ( selected_cell_types . begin ( ) , selected_cell_types . end ( ) , args [ argidx ] ) = = 0 )
selected_cell_types . push_back ( args [ argidx ] ) ;
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}
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if ( ! ilang_file . empty ( ) ) {
if ( ! selected_cell_types . empty ( ) )
log_cmd_error ( " Do not specify any cell types when using -f. \n " ) ;
selected_cell_types . push_back ( " ilang " ) ;
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}
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if ( selected_cell_types . empty ( ) )
log_cmd_error ( " No cell type to test specified. \n " ) ;
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std : : vector < std : : string > uut_names ;
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for ( auto cell_type : selected_cell_types )
for ( int i = 0 ; i < num_iter ; i + + )
{
RTLIL : : Design * design = new RTLIL : : Design ;
if ( cell_type = = " ilang " )
Frontend : : frontend_call ( design , NULL , std : : string ( ) , " ilang " + ilang_file ) ;
else
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create_gold_module ( design , cell_type , cell_types . at ( cell_type ) , constmode , muxdiv ) ;
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if ( ! write_prefix . empty ( ) ) {
Pass : : call ( design , stringf ( " write_ilang %s_%s_%05d.il " , write_prefix . c_str ( ) , cell_type . c_str ( ) + 1 , i ) ) ;
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} else if ( edges ) {
Pass : : call ( design , " dump gold " ) ;
run_edges_test ( design , verbose ) ;
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} else {
Pass : : call ( design , stringf ( " copy gold gate; cd gate; %s; cd ..; opt -fast gate " , techmap_cmd . c_str ( ) ) ) ;
if ( ! nosat )
Pass : : call ( design , " miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter " ) ;
if ( verbose )
Pass : : call ( design , " dump gate " ) ;
Pass : : call ( design , " dump gold " ) ;
if ( ! nosat )
Pass : : call ( design , " sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter " ) ;
std : : string uut_name = stringf ( " uut_%s_%d " , cell_type . substr ( 1 ) . c_str ( ) , i ) ;
if ( vlog_file . is_open ( ) ) {
Pass : : call ( design , stringf ( " copy gold %s_expr; select %s_expr " , uut_name . c_str ( ) , uut_name . c_str ( ) ) ) ;
Backend : : backend_call ( design , & vlog_file , " <test_cell -vlog> " , " verilog -selected " ) ;
Pass : : call ( design , stringf ( " copy gold %s_noexpr; select %s_noexpr " , uut_name . c_str ( ) , uut_name . c_str ( ) ) ) ;
Backend : : backend_call ( design , & vlog_file , " <test_cell -vlog> " , " verilog -selected -noexpr " ) ;
uut_names . push_back ( uut_name ) ;
}
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if ( ! noeval )
run_eval_test ( design , verbose , nosat , uut_name , vlog_file ) ;
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}
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delete design ;
}
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if ( vlog_file . is_open ( ) ) {
vlog_file < < " \n module testbench; \n " ;
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for ( auto & uut : uut_names )
vlog_file < < stringf ( " %s %s (); \n " , uut . c_str ( ) , uut . c_str ( ) ) ;
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vlog_file < < " initial begin \n " ;
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for ( auto & uut : uut_names )
vlog_file < < " " < < uut < < " .run; \n " ;
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vlog_file < < " end \n " ;
vlog_file < < " endmodule \n " ;
}
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}
} TestCellPass ;
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PRIVATE_NAMESPACE_END