Commit Graph

53 Commits

Author SHA1 Message Date
marwaneltoukhy 6402a79dbd updated caravel and caravan mag views to fix the default block issues 2022-11-10 16:15:23 -08:00
Marwan Abbas b239e93992 merged antenna_fix branch and regenrated the views 2022-11-10 06:42:30 -08:00
passant5 0c9e3a08fd
update caravel with tying `porb_h_in` with `por_l_in` (#326)
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`

* add caravel-eco.gds (same as caravel.gds)
2022-10-21 11:52:00 -07:00
Marwan Abbas 71b1faabc5
Caravel final views (#310)
* added views for each step of generating final caravel.gds

* generated the right caravel and caravel-eco gds

* renamed caravel_signoff and removed caravel-non-eco

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-10-19 18:27:26 -07:00
Marwan Abbas bbb6bf775c
Caravel redesign new top (#300)
* reharden: caravel

~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing

* update pdn for `caravel_clocking` & `digital_pll`

* added script to update and generate the power routing views

* ~ run update_power_routing_views from the caravel root with prboundary

* fix output message

* added power routing lef, mag and gds

* fix update_power_routing_views saving wrong cell name

* reharden: caravel

~ incorperate pdn changes
~ re-extract spefs

* fix caravel_power_routing views

* fix abs path in maglef views

* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect

* generate a new chip_io gds

* regenerate gpio_control_block due to mag and gds not in sync

* reharden: caravel

~ change config to pass clean routing
~ use updated views of macros

* lvs clean views

* add caravel top-level generated sdf for all corners

* fix absolute path for mgmt_core_wrapper

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
2022-10-18 17:24:07 -07:00
Tim Edwards 714fc1cd13 Fixes to chip_io to fix LVS issues. Also added back top level
pins on the pads, and reinstated the script that does that from
another branch that was not merged.
2022-10-18 10:29:43 -04:00
kareem a8794dff4b reharden: caravel
~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
kareem 2409207178 reharden: caravel
~ add non functional blocks - like caravel_motto
2022-10-16 15:44:27 -07:00
kareem 704f19b6c7 reharden: caravel
~ correct placement for spare_logic_block
~ add changes from buffering macro
2022-10-16 12:56:41 -07:00
kareem fc0701003c reharden: caravel
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
2022-10-16 06:58:46 -07:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
kareem 9ccb0ff2ed reharden!: caravel
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
2022-10-12 04:45:08 -07:00
kareem 285ef6b642 reharden!: caravel
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
2022-10-10 04:51:05 -07:00
Tim Edwards 7276623d3c Corrected the pull-up definition and revised the CSB definition to
match the corrected defintions (namely, pull-up is configuration
0x0801, and pull-down is configuration 0x0c01).
2022-10-05 10:02:24 -04:00
Tim Edwards aba145e0e2 Made modifications in support of changing the hard-coded default
configuration of GPIO 3 (CSB) from a standard input to a weak
pull-up input.
2022-09-27 20:58:57 -04:00
sto6 9949306c42
issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110)
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.

Co-authored-by: Risto Bell <rb@efabless.com>
2022-08-26 23:03:00 -07:00
R. Timothy Edwards d882f42803
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90)
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
    3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
    make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
    xschem-generated schematic netlist.

NOTE: None of these modifications change the function of any circuit.  The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate.  This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled.  It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.

* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).

* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
2022-05-08 22:51:29 -07:00
Marwan Abbas 6cfedf89a2
fixed caravel netlist to use the 1803 defaults block (#94)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-05-03 10:36:11 -07:00
R. Timothy Edwards 2741111106
Quick fix to a layout route for DRC (#84)
* Quick fix to a route that was hand-corrected from an Openlane
short but which is just shy of the minimum width for metal4.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-22 15:10:31 -07:00
R. Timothy Edwards 99518acd15
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76)
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment.  (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block).  (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells.  (4) Fixed the four
missing routes on the Caravan top level.  (5) Reinstated the large rendered
labels for the pads on both caravel and caravan.  (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper.  (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules.  (9) Moved all
of the LVS scripts to the scripts directory.

* Apply automatic changes to Manifest and README.rst

* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py.  So it's easier to
just manually add them to this pull request.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 19:05:27 -07:00
Tim Edwards 680353f7a7 This corrects a shorted net in the caravel top level layout.
Still evaluating why the layout does not pass LVS like it did
previously, although all current LVS errors appear to be related
to magic's extraction of the isolated substrates, and do not
imply functional issues.  Also, LVS has only been done on the
top level.
2022-04-09 14:23:19 -04:00
Kareem Farid c84e1393e7
updates to top level caravel (#59)
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
2022-04-08 09:31:33 -07:00
D. Mitch Bailey 35781987e1 Correct gpio_defaults_block_34 instance name in caravel.mag 2022-03-14 15:04:14 -07:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock"
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 19:38:24 -05:00
Tim Edwards 2691903104 Reworked part of the layouts of both caravel and caravan to move
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL.  This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
2021-12-02 20:45:39 -05:00
Tim Edwards 0f90c813ed Added a missing route that was not completed in the previous layout
update.  Also changed the defaults block types in the layout so that
they match the gate-level netlist.  This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
2021-11-30 14:38:25 -05:00
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
Tim Edwards 84c97b74b2 Corrected the instance names in the layout so that they once again
correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 19:57:33 -05:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
2021-11-27 11:51:30 -05:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired
it to the power supply, and checked top-level LVS.
2021-11-24 16:50:22 -05:00
Tim Edwards 0114df40ae Added additional power routing from the sides of Caravel to the
user project power ring.  If that is incompatible with user
projects and/or the XOR check, then this commit might need to be
reverted.
2021-11-23 16:49:23 -05:00
Tim Edwards 0ba8884b00 Added a motto for each chip. Just because. 2021-11-23 15:19:41 -05:00
Tim Edwards 5d3f2a26f4 Corrected the Caravel layout and the Caravel and Caravan GL netlists
to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side.  Caravel is now LVS clean again (Caravan needs layout
work).
2021-11-23 11:47:17 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
Tim Edwards cd68a2aeff Made several corrections to errors found in the netlists: (1)
Fixed rstb_h, which was being input to low-voltage blocks.  (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be;  the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line.  This should probably be addressed in
housekeeping but would change the current pinout.
2021-11-22 15:21:06 -05:00
Tim Edwards 515b5a54f2 Updates for LVS. Only LVS issue remaining for caravel is how to get the
ground domains to extract independently.
2021-11-22 12:00:55 -05:00
Tim Edwards 1eb023d973 Added isolated substrate markers in mgmt_protect_hv, should fix the
last of the LVS issues.
2021-11-21 23:04:45 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
2021-11-21 22:58:39 -05:00
Tim Edwards 5262f35610 Modifications done as part of LVS on the caravel top level. 2021-11-21 22:07:16 -05:00
Tim Edwards d87d60cb9b Finished first draft of the caravel power routing (prior to LVS). 2021-11-21 12:41:46 -05:00
Tim Edwards 29dbc77591 More power routing, still a work in progress. 2021-11-20 22:53:18 -05:00
Tim Edwards 6570429234 Continued work on the power routing. Also updated the management
core wrapper view with the LEF view from caravel_pico.
2021-11-20 22:04:46 -05:00
Tim Edwards 8f75362f82 Start of power routing. 2021-11-20 18:04:43 -05:00
Tim Edwards b0d3217280 Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block).  Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there.  Reinstated the copyright, user ID text, open source
logo, and Caravel logo.  Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
2021-11-20 13:43:49 -05:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest
hardened macro components into the caravel and caravan layouts.
2021-11-15 10:34:52 -05:00
Tim Edwards 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new
caravan logo layout.  Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
2021-11-12 16:12:12 -05:00
Tim Edwards 46dd9493f6 Removed some vestiges of top-level routing that were left over
from the previous version of the caravel and caravan layouts.
2021-11-12 13:45:58 -05:00