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653 Commits

Author SHA1 Message Date
Jeff DiCorpo 3aaad6cdf8
Merge pull request #13 from efabless/move_rectify 
Move Rectify To Caravel
 2022-01-18 23:12:52 -08:00
Jeff DiCorpo 14871f91c0
Merge pull request #9 from efabless/documentation_update 
Documentation update
 2022-01-18 23:10:35 -08:00
Donn 641096e4ed Move Rectify To Caravel 2022-01-15 23:27:38 +02:00
Manar f6514b37f3
Update openlane.md 2022-01-14 11:27:37 -05:00
manarabdelaty 4773c5c3f8 Merge branch 'doc' of https://github.com/Manarabdelaty/caravel-1 into doc 2022-01-14 10:33:44 -05:00
manarabdelaty c96a65d023 Update doc 2022-01-14 10:33:15 -05:00
Manar a36d0a68fd
Update openlane.md 2022-01-14 10:25:30 -05:00
manarabdelaty 7083c96e34 Add documentation 2022-01-14 10:05:34 -05:00
Jeff DiCorpo d7b6b40969
Merge pull request #8 from efabless/open_pdks_264 
update open_pdks to 264
 2022-01-10 07:46:30 -08:00
Jeff DiCorpo ae736b84d1
Merge pull request #10 from efabless/fix-gitaction-caravel-lite 
Update auto-update-caravel-lite.yml
 2022-01-10 07:46:04 -08:00
Jeff DiCorpo 86a1e55238
Merge pull request #12 from efabless/dont_compress_oas 
Update Makefile
 2022-01-10 07:45:48 -08:00
Jeff DiCorpo ed71b5f548
Update Makefile 
exclude oas directory from compression
 2022-01-09 17:26:30 -08:00
Jeff DiCorpo ace8cc7f4e
Update auto-update-caravel-lite.yml 2022-01-07 09:04:04 -08:00
Jeff DiCorpo 9f2a1d5f1d
Merge pull request #7 from Manarabdelaty/update_timing_targets 
Update timing targets to run at the three corners
 2022-01-06 13:48:39 -08:00
Jeff DiCorpo 853e7ad841
Merge pull request #4 from marwaneltoukhy/main 
Converting text files in doc/other
 2022-01-06 13:47:16 -08:00
Jeff DiCorpo 25debd801c
Update Makefile 2022-01-06 11:08:42 -08:00
Tim Edwards 2f6fe69b36 Corrected the gen_gpio_defaults.py script so that it behaves 
correctly no matter how the "gpio_defaults_block.mag" and
"gl/gpio_defaults_block.v" are defined.  Previously it assumed
that they both defined all bits as zero, which was not the case
for the layout.  Now both define bit value 0x0402 and the script
can flip bits either direction as needed in both verilog and
layout
 2021-12-29 15:42:41 -05:00
manarabdelaty 7880a52d13 Update timing targets to run at the three corners 2021-12-29 19:11:13 +02:00
Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as 
it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared.  This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
 2021-12-29 11:24:17 -05:00
Marwan Abbas b6e15baec9 added rst dir and converted all docs/other/*.txt to .rst 2021-12-27 19:17:32 +02:00
Marwan Abbas 6648513a0e
Update clamp_list.rst 2021-12-27 19:09:18 +02:00
Marwan Abbas ccce8a0f21
Create power_control.rst 2021-12-27 17:29:46 +02:00
Marwan Abbas 9470db9021
Create management_protect.rst 2021-12-27 17:23:17 +02:00
Marwan Abbas 45c2c643f5
Merge branch 'efabless:main' into main 2021-12-27 17:11:10 +02:00
Marwan Abbas 0b17ee1d77
Create gpio.rst 2021-12-27 17:10:59 +02:00
jeffdi e938b7dcf3 Apply automatic changes to Manifest and README.rst 2021-12-27 00:00:00 +00:00
Jeff DiCorpo 86483ed394
Merge pull request #3 from efabless/fix_tri_state_nets 
Fix tri state nets
 2021-12-26 15:59:23 -08:00
Jeff DiCorpo 1b69f875ec
Merge pull request #2 from d-m-bailey/typo 
user_project_analog_wrapper -> user_analog_project_wrapper
 2021-12-26 15:58:00 -08:00
Marwan Abbas bd2b1becc5
Create caravel_vs_caravan.rst 2021-12-26 18:20:04 +02:00
Marwan Abbas a50de44989
Merge branch 'efabless:main' into main 2021-12-26 17:23:12 +02:00
Tim Edwards 1b3fe4379c Corrected the placement of the isosub layer in the layouts so that 
it is exactly overlapping;  this resolves issues with LVS.  Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
 2021-12-24 22:22:23 -05:00
Mitch Bailey f844f86e81
user_project_analog_wrapper -> user_analog_project_wrapper 2021-12-25 08:16:58 +09:00
manarabdelaty e408d08f93 [DATA] Update gpio_control_block 2021-12-24 22:53:42 +02:00
manarabdelaty dc5d47c812 Merge remote-tracking branch 'origin/main' into fix_tri_state_nets 2021-12-24 22:20:11 +02:00
manarabdelaty 06f05bd296 [DATA] Update mgmt_protect block (lvs clean mag/gds) 2021-12-24 22:19:00 +02:00
manarabdelaty 0225f6b69c [DATA] Update mgmt_core mag/gds to add isosubstrate on the mgmt_protect_hv 2021-12-24 21:51:25 +02:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
Tim Edwards 1526214cc1 Modifications to some of the Makefiles to make the specific RISC-V 
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
 2021-12-24 13:42:36 -05:00
RTimothyEdwards b553b39f5f Apply automatic changes to Manifest and README.rst 2021-12-24 16:48:26 +00:00
Tim Edwards 55836db2d2 Added a reference to the new file "gl/mgmt_defines.v" in the 
caravel_pico repository.  The issue is that each SoC implementation
defines its own modules and therefore needs its own includes.  The
implication is that this file now needs to exist in every SoC
implementation's verilog/gl/ directory.
 2021-12-24 11:46:34 -05:00
Tim Edwards 28931e7968 Added more documentation, fully documenting the GPIO, and various 
aspects of the memory mapped controls for the management protection,
and the various differences between the Caravel and Caravan chips.
 2021-12-23 11:54:36 -05:00
Marwan Abbas 0792dc6930
Create memory_map.rst 2021-12-23 14:41:53 +02:00
Marwan Abbas 56110e66e8
Create gpio_configuration.rst 2021-12-23 14:12:48 +02:00
Marwan Abbas 027dfe8d23
Create clamp_list.rst 2021-12-23 13:53:12 +02:00
Marwan Abbas 070e178c31
Update digital_locked_loop.rst 2021-12-23 13:38:01 +02:00
Marwan Abbas 7d3a8de7b9
Create digital_locked_loop.rst 2021-12-23 12:25:41 +02:00
Jeff DiCorpo 4189166cc9
Update Makefile 
update OPEN_PDKS_COMMIT to 1.0.255
 2021-12-22 12:05:09 -08:00
Jeff DiCorpo 6b61d51f8b
Merge pull request #1 from Manarabdelaty/update_spice 
Update spice netlists to include power routing
 2021-12-22 09:20:16 -08:00
Tim Edwards 31e3d9c106 Started a set of text documents to describe all of the register sets 
and describe the various functions of Caravel (especially housekeeping).
This should eventually be formatted to match the rest of the
documentation.
 2021-12-21 20:00:29 -05:00
manarabdelaty ee0950fdb9 Update spice netlists to include power routing 2021-12-21 19:34:43 +02:00