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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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# distributed under the License is distributed on an "AS IS" BASIS,
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====================
Caravel vs. Caravan
====================
-----------
Caravel
-----------
The Caravel chip user project can use the GPIO pins as analog signals,
and this is the preferred method, as the GPIO pins have ESD protection
on them.
The restrictions on the use of GPIO pins for analog are the following:
(1) The voltage range of the analog signal must be between ``VSSIO`` and
``VDDIO``. On the demonstration board shipped with Caravel, ``VDDIO`` will
be set to ``3.3V`` from an external voltage regulator. However, ``VDDIO``
may be anywhere in the range of ````1.8V```` to ``5.5V``.
(2) The frequency range of the GPIO pads is ``0`` to ``60MHz``
(3) Analog signals should be connected to the ``analog_io`` pins of the user
project wrapper. This pin connects to the pad through a 120 ohm
resistor, for ESD protection. However, it is recommended to place a
diode close to the terminus in the user project circuit for any input
signal that is not otherwise connected to diffusion, for additional
ESD protection. This resistance should be included in system-level
simulations.
(4) When an analog signal is connected to a GPIO pad, the input and
output buffers of the GPIO pad should be turned off, by setting the
GPIO configuration to ``GPIO_MODE_USER_STD_ANALOG`` (see defs.h).
Ideally, the buffers should be turned off by default on chip power-up,
which is done by applying the same configuration in the ``user_defines.v``
file. This ensures that the digital buffers will never be turned on
for those GPIOs.
(5) Analog signals may not use GPIO ``0 to 6 or GPIO 36 and 37``. This prevents
the critical signals such as debug, housekeeping SPI, and flash QSPI
mode pins from being unable to operate due to a constant analog signal
being present on the pad. Therefore there are up to 28 GPIO pins that
can be used for analog signaling.
Note that the signal names ``analog_io[27:0]`` are shifted relative to the
GPIO pad names (mprj_io). So analog_io[0] connects to ``mprj_io[7]``, and
so forth up to ``analog_io[27]`` which connects to ``mprj_io[34]``.
---------
Caravan
---------
In the case that a pin is needed that requires voltages above ``5.5V``, below
``0.0V``, has a frequency higher than ``60MHz``, or cannot tolerate the ``120 ohm``
series resistance, then the Caravan chip provides 11 pads which are
straight-through connections from core to pad. These pads replace pads
``mprj_io[14]`` to ``mprj_io[24]`` and extend across the top of the padframe.
**WARNING:**
The analog pads provide NO ESD protection, because the use of
the pads is open-ended and requirements are different for protection of,
say, high voltage, negative voltage, and very high frequency.
All pads other than the 11 that have straight-through connections from
user project to pad are the same pads as used on Caravel, so there are
up to 17 GPIO pins that can be used for analog signaling under the same
restrictions as noted above for Caravel. These pins are given a different
name on Caravan, which is ``user_gpio_analog[17:0]``.
Because analog circuits will often run at ``3.3V``, digital circuitry for
controlling such circuits should use the HVL digital standard cell library
for ``3.3V`` compatibility. These circuits can connect directly to I/O inputs
if the ``io_in_3v3[26:0]`` pins are used. These pins are copies of the GPIO
pin digital inputs in the ``3.3V`` domain. Note, however, that there is no
corresponding GPIO output in the ``3.3V`` domain. ``3.3V`` outputs must be level
converted into the ``1.8V`` domain using, for example, the cell
sky130_fd_sc_hvl__lsbufhv2lv_1, before being connected to either io_out
or io_oeb.
The full correspondence between mprj_io pins and internal connections is
shown below, copied from
``caravel_user_project_analog/verilog/rtl/user_analog_proj_example.v``:
Caravan signal connections to I/O pins:
============ =============================== ============================== ================================
I/O pin user project digital connection user project analog connection optional power clamp connection
============ =============================== ============================== ================================
mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
mprj_io[24] --- user_analog[10] ---
mprj_io[23] --- user_analog[9] ---
mprj_io[22] --- user_analog[8] ---
mprj_io[21] --- user_analog[7] ---
mprj_io[20] --- user_analog[6] clamp_high/low[2]
mprj_io[19] --- user_analog[5] clamp_high/low[1]
mprj_io[18] --- user_analog[4] clamp_high/low[0]
mprj_io[17] --- user_analog[3] ---
mprj_io[16] --- user_analog[2] ---
mprj_io[15] --- user_analog[1] ---
mprj_io[14] --- user_analog[0] ---
mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
============ =============================== ============================== ================================
Three of the eleven stright-through analog connections on the Caravel chip
go to pads which have voltage clamps underneath. A voltage clamp is a
circuit that protects against ESD events by detecting a rapid rise in
voltage on a power supply pad, and enabling a switch that shorts the
power supply to a nearby ground, reducing the event's voltage spike and
shunting current through a path close to the pads and away from sensitive
circuitry. Each clamp has a positive connection (clamp_high) and a negative
connection (clamp_low). Neither of these pins is connected by default. The
clamp_high pin should be connected to a power supply, preferably the one
connected to the pad directly above it. The clamp_low pin should be
connected to a ground return. Due to the nature of the user project wrapper
as a drop-in module, the current shunting path will be much longer than the
ideal short path. Be sure to make this path as wide as practicable.
The clamp circuit is a high-voltage clamp type intended for operation on a
power supply equal to VDDIO, or nominally ``3.3V`` for the demonstration board
(and otherwise within the range of ``1.8V`` to ``5.5V``). Because the I/O voltage
range includes ``1.8V``, this clamp will operate at ``1.8V``. However, it provides
the best ESD protection for ``3.3V`` supplies. It should not be used with any
supply higher than VDDIO.
Because of the large amount of circuitry (the clamp) directly underneath the
pad, the three pads with the clamps are not intended for high-speed use. These
pads are best used for additional power supply inputs to the analog chip.
The three pads that contain clamps are also designed to provide the largest
amount of current, up to 265mA for each pad (see below). The pin connection
at the user project wrapper boundary consists of two ports, 25um wide, each
comprising a stack of metals 3, 4, and 5. To get the maximum current through
the pad without creating electromigration issues, connect to all three metals
on both ports.
Power supply routing on Caravan is expected to be done manually. Allow less
than ``1.5mA`` per micron width on metal3 and metal4 to satisfy electromigration
rules, and less than ``2.3mA`` per micron on metal5. The maximum current per
dedicated power pad is
.. math::
((25um * 2) * (1.5 + 1.5 + 2.3)) = 265mA
Wrapper pins
--------------------------
Due to the way the wrapper circuit is "dropped into" the Caravel or Caravan
harness chip, a continuity check must be run at tape-in to ensure that the
pins of the wrapper connect correctly to the corresponding locations on the
harness. This requires that each pin in the design must be on a unique net.
Because of this requirement, pins in the user wrapper may not be shorted
together, otherwise only one of the shorted pins can be represented as a
subcircuit port in the extracted SPICE netlist.
Because shorting pins together is a likely use case, especially in analog
designs, the recommended procedure when connecting pins together is to
place a "metal resistor" in front of the pin connection on all connections
other than the primary one. Most pin connections are on metal3, so a
metal3 resistor is preferred. The "metal resistor" in the layout is an
identifying layer, not a mask layer, so the metal should be continuous
through to the connection, with the resistor identifier layer spanning the
width of the connection.
For example, the user may want to tie together VDDA1 and VDDA2 to double
the current capacity of the ``3.3V`` domain power supply. The user should
route a power bus and connect it directly to the VDDA1 pin. Then, a
route can be made to the VDDA2 pin but should pass through a metal3
resistor before making the connection to the pin. Any such resistor
must be represented as a device in a schematic drawing for the design to
pass LVS.
Allocating power supplies
--------------------------
As mentioned above, power supplies may be connected together if needed.
These are the available power supplies:
- VCCD1/VSSD1 : User domain 1, ``1.8V`` power
- VCCD2/VSSD2 : User domain 2, ``1.8V`` power
- VDDA1/VSSA1 : User domain 1, ``3.3V`` power
- VDDA2/VSSA2 : User domain 2, ``3.3V`` power
- VDDIO/VSSIO : Management domain, ``3.3V`` power supply to padframe
- VCCD/VSSD : Management domain, ``1.8V`` power supply to padframe and SoC
All pad connections that are chip pins are in the VDDIO domain. All low
voltage pad connections to the chip core are in the VCCD domain, and
the only high voltage pins (io_in_3v3; see above) connected to the user
project wrapper are in the VDDIO domain.
Any of the user power supplies that are in the same power domain can be
connected together to provide additional current capacity. So VCCD1 and
VCCD2 may be connected together (along with connecting together VSSD1
and VSSD2); and VDDA1 and VDDA2 may be connected together (along with
VSSA1 and VSSA2). The user project does not have direct access to the
management area power domains, including the supplies that drive the
padframe I/O.

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.. raw:: html
<!---
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-->
=========================
Clamp List
=========================
============================ =========================== ====== ====== ====== ====== =====
Pad Instance Clamp connections
---------------------------- --------------------------- ---------------------------------
-- -- DRN1 SRC1 DRN2 SRC2 B2B
============================ =========================== ====== ====== ====== ====== =====
sky130_ef_io__vddio_hvc_pad \mgmt_vddio_hvclamp_pad[0] vddio vssio
sky130_ef_io__vddio_hvc_pad \mgmt_vddio_hvclamp_pad[1] vddio vssio
sky130_ef_io__vssio_hvc_pad \mgmt_vssio_hvclamp_pad[0] vddio vssio
sky130_ef_io__vssio_hvc_pad \mgmt_vssio_hvclamp_pad[1] vddio vssio
sky130_ef_io__vdda_hvc_pad mgmt_vdda_hvclamp_pad vdda vssa
sky130_ef_io__vssa_hvc_pad mgmt_vssa_hvclamp_pad vdda vssa
sky130_ef_io__vdda_hvc_pad user1_vdda_hvclamp_pad vdda1 vssa1
sky130_ef_io__vssa_hvc_pad user1_vssa_hvclamp_pad vdda1 vssa1
sky130_ef_io__vdda_hvc_pad user2_vdda_hvclamp_pad vdda2 vssa2
sky130_ef_io__vssa_hvc_pad user2_vssa_hvclamp_pad vdda2 vssa2
sky130_ef_io__vccd_lvc_pad mgmt_vccd_lvclamp_pad vccd vssio vccd vssd vssa
sky130_ef_io__vssd_lvc_pad mgmt_vssd_lvclmap_pad vccd vssio vccd vssd vssa
sky130_ef_io__vccd_lvc_pad user1_vccd_lvclamp_pad vccd1 vssd1 vccd1 vssd vssio
sky130_ef_io__vssd_lvc_pad user1_vssd_lvclmap_pad vccd1 vssd1 vccd1 vssd vssio
sky130_ef_io__vccd_lvc_pad user2_vccd_lvclamp_pad vccd2 vssd2 vccd2 vssd vssio
sky130_ef_io__vssd_lvc_pad user2_vssd_lvclmap_pad vccd2 vssd2 vccd2 vssd vssio
============================ =========================== ====== ====== ====== ====== =====
Overlay types used:
===================
1. hvc_pad: vddio -> vssio
2. hvc_pad: vdda -> vssa
3. lvc_pad: vccd -> vssio, vccd -> vssd vssa
4. lvc_pad: vccd -> vssd, vccd -> vssdG vssio
**NOTE:**
Type (4) crosses domains, so that the local VCCD has a diode to the
local VSSD and also to the global VSSD. **BUT:** Although vccd goes all the way
around the chip in the form of vcchib, vssd does not, which makes the SRC2
connection effectively unreachable in this configuration, so better to just
change it to vssd1 and vssd2 for the respective domains.
New overlay types created:
==========================
1. sky130_ef_io__vddio_hvc_clamped_pad: sky130_ef_io__vddio_hvc_pad + overlay (1)
2. sky130_ef_io__vssio_hvc_clamped_pad: sky130_ef_io__vssio_hvc_pad + overlay (1)
3. sky130_ef_io__vdda_hvc_clamped_pad: sky130_ef_io__vdda_hvc_pad + overlay (2)
4. sky130_ef_io__vssa_hvc_clamped_pad: sky130_ef_io__vssa_hvc_pad + overlay (2)
5. sky130_ef_io__vccd_lvc_clamped_pad: sky130_ef_io__vccd_lvc_pad + overlay (3)
6. sky130_ef_io__vssd_lvc_clamped_pad: sky130_ef_io__vssd_lvc_pad + overlay (3)
7. sky130_ef_io__vccd_lvc_clamped2_pad: sky130_ef_io__vccd_lvc_pad + overlay (4)
8. sky130_ef_io__vssd_lvc_clamped2_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
9. sky130_ef_io__vccd_lvc_clamped3_pad: sky130_ef_io__vccd_lvc_pad + overlay (4)
10. sky130_ef_io__vssd_lvc_clamped3_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
**NOTE:**
The ``clamped3`` pads correspond to a change in the Caravel design for MPW-2,
in which the vccd/vssd domain has continuous supply rings around the chip
periphery. The pad connection of these two pads does not connect to the padframe
power rings, but connects to a separate set of power rails in the chip core.

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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
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-->
===========================
Caravel digital locked loop
===========================
The Caravel digital locked loop ``DLL`` is an all-digital clock generating
module.
The GPIO pins on Caravel have a limit of 50MHz input. Internally, it is
possible to generate a clean oscillation of up to around 200MHz or higher.
To ensure large margins of safety, the Caravel demonstration board ships
with an on-board oscillator of 10MHz. The operational frequency of the
management SoC on Caravel differs according to which management SoC
architecture is present, but is generally in the range of around 50MHz.
The DLL comprises an on-chip tunable ring oscillator and a feedback
controller for locking to a known input clock. It can operate in either
free-running ``DCO`` or locked ``DLL`` modes. The Caravel system can run
directly off of the external clock (bypass mode), the free-running DCO,
or the DLL locked to the external clock.
The DLL's tunable oscillator has an operating range of approximately
75MHz to 150MHz. The oscillator is a loop of from 13 to 39 inverter
stages with 26 bits of trim. Each trim bit adds or subtracts one of
the stages. So there are 27 effective frequency steps covering a range
of about 75MHz, with an incremental delay of about 250ps per step.
In the Caravel memory map, the DLL is controlled by a handful of registers
as shown below. These registers are in the housekeeping SPI module, and
so can be controlled either from an external source through the housekeeping
SPI, or internally through the management SoC.
**WARNING:**
The management SoC altering its own clock has not yet been tested
as of this writing; however, the core clock should be guaranteed to be glitch-
free through transistions from external clock to DLL output and vice versa.
-------------
DLL operation
-------------
The DLL operates by taking the ring oscillator output, reducing its frequency
through a feedback divider, and comparing the result to the input clock.
If the frequency of the divided-down ring oscillator output is faster than
the input clock frequency, then an additional delay stage is added to the
ring oscillator, making it run slower. If the frequency of the divided-down
ring oscillator output is slower than the input clock frequency, then a delay
stage is subtracted from the ring oscillator, making it faster. This
operation is performed in a continuous loop to keep the DLL frequency locked
to the input clock.
**WARNING:**
Using discrete delay state insertion and removal results in high
phase noise (cycle to cycle jitter) on the core clock when running in DLL mode,
due to instantaneous changes of 250ps between cycles (a 0.25% change in the
clock period). User projects that require a clock with low phase noise should
use the external clock (DLL in bypass mode), and if the project requires a
higher clock rate, then the 10MHz clock on the demonstration board may be
replaced with another oscillator of the same footprint with a frequency up
to 50MHz. The DLL running in DCO mode has low cycle-to-cycle jitter but will
have a large drift component, as it is not temperature stabilized.
The DLL controls are memory-mapped to the housekeeping space, and are as follows:
=================================================================================
- Register name = ``reg_hkspi_pll_ena``
- Memory location = ``0x2610000c``
- Housekeeping SPI location = ``0x08``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x09 | | | | | | | DCO | DLL |
| | | | | | | | ena | ena |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bit 1: DCO enable
value 0 = DCO disabled. DLL runs in active locking mode
value 1 = DCO enabled. DLL runs in DCO mode.
bit 0: DLL enable
value 0 = DLL disabled. DLL is disabled and the clock is stopped.
value 1 = DLL enabled. DLL is enabled and outputs a clock.
=============================================================================
- Register name = ``reg_hkspi_pll_bypass``
- Memory location = ``0x26100010``
- Housekeeping SPI location = ``0x09``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x09 | | | | | | | | DLL |
| | | | | | | | | bypass|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bit 0: DLL bypass
value 0 = DLL active. Core clock is derived from the DLL output.
value 1 = DLL bypassed. Core clock is derived from the external clock source.
=============================================================================
- Register name = ``reg_hkspi_pll_trim``
- Memory location = ``0x2610001c to 0x261001f``
- Housekeeping SPI location = ``0x0d to 0x10``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x10 | | | | | | | trim25| trim24|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0f | trim23| trim22| trim21| trim20| trim19| trim18| trim17| trim16|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0e | trim15| trim14| trim13| trim12| trim11| trim10| trim9 | trim8 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0d | trim7 | trim6 | trim5 | trim4 | trim3 | trim2 | trim1 | trim0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
**All bits:**
DLL manual trim value. This 26-bit value is applied to
the DLL when in DCO mode and directly controls the frequency
of the ring oscillator. Each '1' bit turns on one delay
stage in the oscillator.
**NOTE:**
The phase relationship between the DLL outputs (for the core
clock and the user clock) is nominally 90 degrees when the trim
stages are balanced along the length of the oscillator, but this
phase can be altered with non-uniform delays.
=============================================================================
- Register name = ``reg_hkspi_pll_divider``
- Memory location = ``0x26100024``
- Housekeeping SPI location = ``0x12``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x12 | | | | div4 | div3 | div2 | div1 | div0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bits 4 to 0: Value of the DLL feedback divider. In active DLL mode,
the DLL output is divided down by this amount, and then the
trim is adjusted to make the divided value match the incoming
external clock.
For example, if the external clock is 10MHz and the divider value is
9 (div = 5'b01001), then the DLL will trim the oscillator to run at
10MHz * 9 = 90MHz. The value of (external clock frequency * divider
value) must always be within the DLL's trimmable range, or else the
DLL will saturate.
=============================================================================
- Register name = ``reg_hkspi_pll_source``
- Memory location = ``0x26100020``
- Housekeeping SPI location = ``0x11``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x11 | | | core2 | core1 | core0 | user2 | user1 | user0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bits 2 to 0: Value of the user clock output divider. The value of
the secondary clock ("user_clock") in the user project area
is derived from the zero-phase ring oscillator output divided
down by this amount. The values range from 1 (divide by 1)
to 7 (divide by 7).
bits 5 to 3: Value of the core clock output divider. The value of
the primary clock ("wb_clk_i") in the user project area
is derived from the 90-degree-phase ring oscillator output
divided down by this amount. The values range from 1 (divide
by 1) to 7 (divide by 7).

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=============
Caravel GPIO
=============
The Caravel GPIO pins are multi-purpose pins capable of being configured
for numerous applications, including digital input, output, analog
signaling, with slew rate control, transition level control, and weak
pull-up and pull-down functions.
The GPIO pins are configured to operate either under the control of the
Caravel management SoC or under the control of the user project. When
used under management SoC control, certain pins have certain special
functions.
--------------------------------------------------------------------------
- Register name = ``reg_mprj_io_0``
- Memory location = ``0x26000024``
- Housekeeping SPI location = ``0x1d, 0x1e``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x1e |analog |analog |analog | mode |input | hold | output| mgmt |
| |polar. |select |enable | select|disable| over | enb | enable|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x1d | | | |digital|digital|digital| trip | slow |
| | | | |mode 0 |mode 1 |mode 2 | point | slew |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: Management enable (bit field ``MGMT_ENABLE``)
- value 0 = User project controls the GPIO pin
- value 1 = Management SoC controls the GPIO pin
*bit 1*: Output enable bar (output disable) (bit field ``OUTPUT_DISABLE``)
- value 0 = Pad enabled for digital output
- value 1 = Pad disabled for digital output
*bit 2*: Holdover (bit field ``HOLD_OVERRIDE``)
- value 0 = all I/O latched during hold mode
- value 1 = only inputs latched during hold mode
**NOTE:**
The GPIO cannot be placed in hold mode in this version of Caravel.
*bit 3*: Input disable (bit field ``INPUT_DISABLE``)
- value 0 = Pin enabled for digital input
- value 1 = Pin disabled for digital input
*bit 4*: Input buffer Mode select (bit field ``MODE_SELECT``)
- value 0 = CMOS/LVTTL mode (see trip point value, below)
- value 1 = Input buffer compliant with 1.8V external signals ``VIL = 0.54V``; ``VIH = 1.26V``. Overrides the trip point setting.
*bit 5*: Analog enable (bit field ``ANALOG_ENABLE``)
- value 0 = analog busses disconnected
- value 1 = analog busses connected
The analog function is intended for a type of switched-capacitor operation on the inputs. Its use is limited in Caravel.
*bits 6-7*: Analog select and polarity (bit field ``ANALOG_SELECT`` | ``ANALOG_POLARITY``)
- (value = ``{out, bit[7], bit[6], out}`` in the list below)
- value 000 = connect pad to VSSIO
- value 001 = connect pad to analog A bus
- value 010 = connect pad to VSSIO
- value 011 = connect pad to analog B bus
- value 100 = connect pad to analog A bus
- value 101 = connect pad to VDDIO
- value 110 = connect pad to analog B bus
- value 111 = connect pad to VDDIO
*bit 8*: Slow slew (bit field ``SLOW_SLEW_MODE``)
- value 0 = Fast output slew rate
- value 1 = Slow output slew rate
*bit 9*: Trip point (bit field ``TRIPPOINT_SEL``)
- value 0 = CMOS (VIL = 0.3 * VDDIO; VIH = 0.7 * VDDIO)
- value 1 = LVTTL (VIL = 0.8V; VIH = 2.0V)
The value determines what input voltage is converted to a
0 or 1 bit by the input buffer. Value 0 is appropriate
for CMOS operation; value 1 is appropriate for ``LVTTL``
operation. When the VDDIO power supply is less than ``2.7V``,
then the trip point is always in CMOS mode. See also
the input buffer mode select, above.
*bits 10-12*: Digital mode (bit field ``DIGITAL_MODE_MASK``)
- (value = ``{bit[12], bit[11], bit[10]}`` in the list below)
- value 000 = analog mode
- value 001 = analog mode
- value 010 = digital input, 5kohm pull-up
- value 011 = digital input, 5kohm pull-up
- value 100 = open drain to power
- value 101 = open drain to ground
- value 110 = digital output
- value 111 = digital output (weak)
*The remaining I/O configuration registers have the same form as above.*
The memory mapped addresses are as follows:
-------------------------------------------
- Register name = ``reg_mprj_io_1``, Memory location = ``0x26000028``, Housekeeping SPI location = ``0x1f, 0x20``
- Register name = ``reg_mprj_io_2``, Memory location = ``0x2600002c``, Housekeeping SPI location = ``0x21, 0x22``
- Register name = ``reg_mprj_io_3``, Memory location = ``0x26000030``, Housekeeping SPI location = ``0x23, 0x24``
- Register name = ``reg_mprj_io_4``, Memory location = ``0x26000034``, Housekeeping SPI location = ``0x25, 0x26``
- Register name = ``reg_mprj_io_5``, Memory location = ``0x26000038``, Housekeeping SPI location = ``0x27, 0x28``
- Register name = ``reg_mprj_io_6``, Memory location = ``0x2600003c``, Housekeeping SPI location = ``0x29, 0x2a``
- Register name = ``reg_mprj_io_7``, Memory location = ``0x26000040``, Housekeeping SPI location = ``0x2b, 0x2c``
- Register name = ``reg_mprj_io_8``, Memory location = ``0x26000044``, Housekeeping SPI location = ``0x2d, 0x2e``
- Register name = ``reg_mprj_io_9``, Memory location = ``0x26000048``, Housekeeping SPI location = ``0x2f, 0x30``
- Register name = ``reg_mprj_io_10``, Memory location = ``0x2600004c``, Housekeeping SPI location = ``0x31, 0x32``
- Register name = ``reg_mprj_io_11``, Memory location = ``0x26000050``, Housekeeping SPI location = ``0x33, 0x34``
- Register name = ``reg_mprj_io_12``, Memory location = ``0x26000054``, Housekeeping SPI location = ``0x35, 0x36``
- Register name = ``reg_mprj_io_13``, Memory location = ``0x26000058``, Housekeeping SPI location = ``0x37, 0x38``
- Register name = ``reg_mprj_io_14``, Memory location = ``0x2600005c``, Housekeeping SPI location = ``0x39, 0x3a``
- Register name = ``reg_mprj_io_15``, Memory location = ``0x26000060``, Housekeeping SPI location = ``0x3b, 0x3c``
- Register name = ``reg_mprj_io_16``, Memory location = ``0x26000064``, Housekeeping SPI location = ``0x3d, 0x3e``
- Register name = ``reg_mprj_io_17``, Memory location = ``0x26000068``, Housekeeping SPI location = ``0x3f, 0x40``
- Register name = ``reg_mprj_io_18``, Memory location = ``0x2600006c``, Housekeeping SPI location = ``0x41, 0x42``
- Register name = ``reg_mprj_io_19``, Memory location = ``0x26000070``, Housekeeping SPI location = ``0x43, 0x44``
- Register name = ``reg_mprj_io_20``, Memory location = ``0x26000074``, Housekeeping SPI location = ``0x45, 0x46``
- Register name = ``reg_mprj_io_21``, Memory location = ``0x26000078``, Housekeeping SPI location = ``0x47, 0x48``
- Register name = ``reg_mprj_io_22``, Memory location = ``0x2600007c``, Housekeeping SPI location = ``0x49, 0x4a``
- Register name = ``reg_mprj_io_23``, Memory location = ``0x26000080``, Housekeeping SPI location = ``0x4b, 0x4c``
- Register name = ``reg_mprj_io_24``, Memory location = ``0x26000084``, Housekeeping SPI location = ``0x4d, 0x4e``
- Register name = ``reg_mprj_io_25``, Memory location = ``0x26000088``, Housekeeping SPI location = ``0x4f, 0x50``
- Register name = ``reg_mprj_io_26``, Memory location = ``0x2600008c``, Housekeeping SPI location = ``0x51, 0x52``
- Register name = ``reg_mprj_io_27``, Memory location = ``0x26000090``, Housekeeping SPI location = ``0x53, 0x54``
- Register name = ``reg_mprj_io_28``, Memory location = ``0x26000094``, Housekeeping SPI location = ``0x55, 0x56``
- Register name = ``reg_mprj_io_29``, Memory location = ``0x26000098``, Housekeeping SPI location = ``0x57, 0x58``
- Register name = ``reg_mprj_io_30``, Memory location = ``0x2600009c``, Housekeeping SPI location = ``0x59, 0x5a``
- Register name = ``reg_mprj_io_31``, Memory location = ``0x260000a0``, Housekeeping SPI location = ``0x5b, 0x5c``
- Register name = ``reg_mprj_io_32``, Memory location = ``0x260000a4``, Housekeeping SPI location = ``0x5d, 0x5e``
- Register name = ``reg_mprj_io_33``, Memory location = ``0x260000a8``, Housekeeping SPI location = ``0x5f, 0x60``
- Register name = ``reg_mprj_io_34``, Memory location = ``0x260000ac``, Housekeeping SPI location = ``0x61, 0x62``
- Register name = ``reg_mprj_io_35``, Memory location = ``0x260000b0``, Housekeeping SPI location = ``0x63, 0x64``
- Register name = ``reg_mprj_io_36``, Memory location = ``0x260000b4``, Housekeeping SPI location = ``0x65, 0x66``
- Register name = ``reg_mprj_io_37``, Memory location = ``0x260000b8``, Housekeeping SPI location = ``0x67, 0x68``
The bit value of the 13-bit static configuration GPIO setting is difficult
to remember, so the "defs.h" file (included when compiling a C program for
the management SoC) contains some definitions for typical useful configuration
values, **as follows**:
.. code:: bash
#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
#define GPIO_MODE_USER_STD_OUTPUT 0x1808
#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802
#define GPIO_MODE_USER_STD_ANALOG 0x000a
**Defintion**:
``GPIO_MODE_MGMT_STD_INPUT_NOPULL``:
Management controls the GPIO pin.
Pin is configured as a digital input, no pull-up or pull-down.
``GPIO_MODE_MGMT_STD_INPUT_PULLDOWN``:
Management controls the GPIO pin.
Pin is configured as a digital input with a weak (5k) pull-down.
``GPIO_MODE_MGMT_STD_INPUT_PULLUP``:
Management controls the GPIO pin.
Pin is configured as a digital input with a weak (5k) pull-up.
``GPIO_MODE_MGMT_STD_OUTPUT``:
Management controls the GPIO pin.
Pin is configured as a digital output (output only).
``GPIO_MODE_MGMT_STD_BIDIRECTIONAL``:
Management controls the GPIO pin.
Pin is configured as a digital input or output. The direct
control of the GPIO from the management SoC does not include
bidirectional control, and this should only be set for those
special functions that use bidirectional or tristatable pins
(flash QSPI data pins, housekeeping SDO, SPI master SDO, and
the debug pin).
``GPIO_MODE_MGMT_STD_ANALOG``:
Digital input and output buffers are disabled. The pin has no
function for the management SoC.
``GPIO_MODE_USER_STD_INPUT_NOPULL``:
The user project controls the GPIO pin.
Pin is configured as a digital input, no pull-up or pull-down.
``GPIO_MODE_USER_STD_INPUT_PULLDOWN``:
The user project controls the GPIO pin.
Pin is configured as a digital input with a weak (5k) pull-down.
``GPIO_MODE_USER_STD_INPUT_PULLUP``:
The user project controls the GPIO pin.
Pin is configured as a digital input with a weak (5k) pull-up.
``GPIO_MODE_USER_STD_OUTPUT``:
The user project controls the GPIO pin.
Pin is configured as a digital output (output only).
``GPIO_MODE_USER_STD_BIDIRECTIONAL``:
The user project controls the GPIO pin.
Pin is configured as a digital input or output. The input
(io_in) is always active. The output (io_out) is applied to
the pad only if the corresponding output disable (io_oeb) is
set to zero.
``GPIO_MODE_USER_STD_OUT_MONITORED``:
The user project controls the GPIO pin like
the ``GPIO_MODE_USER_STD_BIDIRECTIONAL`` mode, above; however,
the pad value also appears at the management SoC, so the
management SoC can treat this pad as an input pin, monitoring
the value seen by the user project.
``GPIO_MODE_USER_STD_ANALOG``:
The user project controls the GPIO pin.
Digital input and output buffers are disabled. If the
corresponding analog_io pin is connected to an analog signal
in the user project, then that signal (unbuffered) appears on
the pad.
--------------------------------------------------------------------------
- Register name = ``reg_mprj_xfer``
- Memory location = ``0x26000000``
- Housekeeping SPI location = ``0x13``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x13 | | data | data | clock | load | resetn| enable| xfer/ |
| | | 2 | 1 | | | | | busy |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: xfer / busy
**On reading this bit:**
- value 0 = The serial transfer is idle
- value 1 = The serial transfer is in progress
**On writing this bit:**
- value 0 = No action (the default state)
- value 1 = Initiate a serial transfer of GPIO configuration data from the housekeeping registers to the GPIOs.
*bit 1*: Serial bit-bang enable:
- value 0 = Serial transfer is done by the "xfer" bit.
- value 1 = Serial transfer is done by bit banging.
*bit 2*: Serial bit-bang reset bar:
- value 0 = Reset all GPIO to their default values
- value 1 = No action (the default state)
*(See also the page on setting the default GPIO configuration.)*
*bit 3*: Serial bit-bang load:
- value 0 = No action (the default state)
- value 1 = Simultaneously copy all GPIO configuration data from the shift register to the GPIOs.
*bit 4*: Serial bit-bang clock:
- value 0 = No action (the default state)
- value 1 = Advance data in the serial shift registers by 1 bit
*bit 5*: Serial bit-bang data 1:
value = GPIO configuration for the left side to be shifted on next clock.
*bit 6*: Serial bit-bang data 2:
value = GPIO configuration for the right side to be shifted on next clock.
The GPIO pins are configured through a serial chain that allows the
static configuration setting of each GPIO to be registered close to the
pad and avoid wiring every configuration bit of every pad back to the
management area. The configuration held near the pad is a copy of the
configuration held in the memory mapped registers. The value in the
memory mapped register can be considered a "staging area" value. The
GPIO function will not update until the values are transferred from the
housekeeping registers to the GPIO pad. The function that does this is
the "transfer" bit in this register. The remaining values allow the
serial programming to be done manually by "bit banging". The bit
bang functions should be considered diagnostic only.
In normal (not bit-bang) mode, the "xfer" bit needs to be set to one to
initiate a transfer of data from the memory mapped registers in the
housekeeping module to the GPIOs. The "xfer" bit is self-resetting back
to zero. The value of this bit cannot be read directly. When reading
back this register, the bit 0 position contains the "busy" state of the
serial transfer. This allows the control program for the management SoC
to know when the GPIO pins have been properly configured. The "busy" bit
will be set back to zero after the serial load has occurred.
In "bit-bang" mode, the register is used to directly control the
operation of the serial load instead of the automatic load initiated
by the "xfer" bit. "bit-bang" mode is considered diagnostic, and should
not need to be used. For completeness, its operation is described below:
There are two serial shift registers, one on the left side of the chip
running from ``mprj_io[37]`` to ``mprj_io[19]``, and the other on the right side
of the chip running from ``mprj_io[0]`` to ``mprj_io[18]``. There are 13 bits
per GPIO according to the configuration registers (see above), applied
consecutively and in reverse. So the first value applied to data 2 is
``mprj_io[18]`` configuration bit 12, and the the last value is ``mprj_io[0]``
configuration bit 0, with ``19 * 13 = 247 bits total``. After applying each
data bit, toggle the clock. At the end of 247 clocks, the load bit is
toggled to transfer the data from the shift register to the GPIOs.
General-purpose I/O standard operation:
----------------------------------------
When a GPIO is configured for management control, and the management SoC
is not using that pin for a special function (see special functions,
below), the GPIO pin may be used for bit-wise read and write operations.
The two registers reg_mprj_datal (32 bits) and reg_mprj_datah (6 bits)
together comprise the data registers for direct readback and control of
the GPIO pad values to and from the management SoC. Unlike the static
configuration setting, these values are connected directly to the GPIOs
and update when written.
Note that the registers reg_mprj_datal and reg_mprj_datah are effectively
write-only. Reading from these addresses reads the bit value of the GPIO
pad, not the value stored in the register. There is no method implemented
to read back the value written to these registers.
--------------------------------------------------------------------------
- Register name = reg_mprj_datal
- Memory location = 0x2600000c
- Housekeeping SPI location = 0x6a to 0x6d
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x6d | gpio | gpio | gpio | gpio | gpio | gpio | gpio | gpio |
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x6c | gpio | gpio | gpio | gpio | gpio | gpio | gpio | gpio |
| | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x6b | gpio | gpio | gpio | gpio | gpio | gpio | gpio | gpio |
| | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x6a | gpio | gpio | gpio | gpio | gpio | gpio | gpio | gpio |
| | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
--------------------------------------------------------------------------
- Register name = reg_mprj_datah
- Memory location = 0x26000010
- Housekeeping SPI location = 0x69
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x69 | | | gpio | gpio | gpio | gpio | gpio | gpio |
| | | | 37 | 36 | 35 | 34 | 33 | 32 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
**IMPORTANT NOTE:**
When writing to the GPIO data from the housekeeping
SPI, all writes are done byte-wise. When writing GPIO data from the
management SoC, the lower word (GPIO 0 to 31) is written simultaneously,
and the upper word (GPIO 32 to 37) is written simultaneously. There is
no option at this time to update all 38 GPIO outputs at the same time.
In particular, note that an 8-bit or 16-bit write to the register from
the management SoC that does not include the upper byte will *not*
update, but will save the written value to a temporary register that
will be applied when the upper byte is written. Therefore it is
recommended to always make 32-bit writes to the ``reg_mprj_datal`` register
to avoid unexpected behavior. 8-, 16-, and 32-bit reads on this register
will work as expected.
GPIO under user project control
---------------------------------------------------
When used by the user project, every GPIO is a simple bidirectional digital
pad. The GPIO is configured by the serial transfer method above to behave
as required by the user project. Once configured to user control, the GPIO
can be controlled by three pins:
- io_in[37:0]
- io_out[37:0]
- io_oeb[37:0]
The io_in[..] signals are from the pad to the user project and are always
active unless the pad has been configured with the "input disable" bit set.
The io_out[..] signals are from the user project to the pad.
The io_oeb[..] signals are from the user project to the pad cell. This
controls the direction of the pad when in bidirectional mode. When set to
value zero, the pad direction is output and the value of io_out[..] appears
on the pad. When set to value one, the pad direction is input and the pad
output buffer is disabled.
The exact behavior of these signals depends on the static configuration of
the corresponding GPIO pad. See the predefined user mode definitions,
above.
Dedicated GPIO functions used by the management SoC
---------------------------------------------------
The housekeeping module defines specific GPIOs to be used for special
functions when those GPIOs are under control of the management SoC.
The dual function for each ``mprj_io`` pad is as follows:
``mprj_io[0]`` Debug*
``mprj_io[1]`` housekeeping SDO
``mprj_io[2]`` housekeeping SDI
``mprj_io[3]`` housekeeping CSB
``mprj_io[4]`` housekeeping SCK
``mprj_io[5]`` UART ser_rx
``mprj_io[6]`` UART ser_tx
``mprj_io[7]`` IRQ 1 source
``mrpj_io[8]`` user flash CSB
``mrpj_io[9]`` user flash SCK
``mrpj_io[10]`` user flash IO0
``mrpj_io[11]`` user flash IO1
``mprj_io[12]`` IRQ 2 source
``mprj_io[13]`` Trap monitor**
``mprj_io[14]`` Core clock monitor
``mprj_io[15]`` User clock monitor
``mprj_io[32]`` SPI master SCK
``mprj_io[33]`` SPI master CSB
``mprj_io[34]`` SPI master SDI
``mprj_io[35]`` SPI master SDO
``mprj_io[36]`` flash IO2*
``mprj_io[37]`` flash IO3*
*The Debug and flash QSPI modes may not be available on all management SoC core types.*
**The trap signal may not be implemented on all management SoC core types, and this pin may be connected to a different signal for monitoring, or none at all.**
The 38 GPIO pins are accessed in the following order of precedence:
1. The user project accesses the GPIO whenever the GPIO configuration
"management enable" bit (bit 0) is set to 0, using the 3-wire
interface ``io_in, io_out, io_oeb``.
2. The management SoC accesses the GPIO with a special function when
the GPIO configuration "management enable" bit (bit 0) is set to
1, and the corresponding special function is enabled (see summary
below for the enable bit for each special function).
3. The management SoC accesses the GPIO with the standard GPIO read/
write data function when the GPIO configuration "management enable"
bit (bit 0) is set to 1, and no special function is enabled.
A summary of each dedicated management core function is provided below:
-----------------------------------------------------------------------
**Debug**:
The debug pin enables the debug function on any management SoC core
that supports a debug mode. Its use is open-ended and depends on
the specific core, but a typical use case is that applying a "1"
value to this pin (setting to VDDIO) activates the UART and allows
debugging through the UART port. The debug function is enabled by
the management SoC, and its state is defined by the SoC
implementation. The implementation may choose to set the debug
enable signal high always, in which case the GPIO 0 pin cannot be
used by the management SoC for general-purpose I/O (this does not
affect the use of the pin by the user project).
**Housekeeping SPI**:
GPIO pads 1-4 are dedicated to the housekeeping SPI on power-up and
may not be configured otherwise by default. This allows a 4-pin
diagnostic SPI interface for querying the project ID of the chip and
a number of the internal memory mapped registers, as well as allowing
access to apply a manual interrupt to the CPU, to manually reset the
chip, or to program the SPI flash with the pass-through mode. On the
demonstration board, these pins are connected directly to the FTDI
chip so that the housekeeping SPI can be read and written from a host
computer through USB. They may be reconfigured for use by the user
project; the FTDI can be configured to tristate these pins so that
the user project can use them unconditionally. Generally speaking,
a user project should use these pins as a "last resort". When a
user project controls these pads, the "housekeeping disable" bit
should be set to 1. Likewise, when the management SoC wants to use
these pins for general-purpose I/O, the "housekeeping disable" bit
should be set to 1. Otherwise the housekeeping SPI pins are always
enabled for the special function.
**UART**:
GPIO pads 5 and 6 can be used by the management SoC as a serial UART.
When the UART enable bit is set in the UART control register, these
pins are used for UART Tx and Rx. When the UART enable bit is cleared,
these pins are general purpose I/O. Generally, a user project should
try to keep these pins free for use by the management SoC, since the
UART is the most convenient method for communication between the
management SoC and a host computer.
**SPI master**:
GPIO pads 32 to 35 are the I/O of the SPI master when it is
enabled.
**Flash QSPI**:
For management SoC architectures that support QSPI mode on the
SPI flash controller, the two highest-numbered GPIOs (36 and 37)
will act as data lines IO2 and IO3 when QSPI mode is enabled
on the flash controller.
**Clock monitoring**:
The two primary clocks from the Caravel clock module are the
core clock driving the management SoC, and the user clock, which
is a secondary clock available to the user space that is derived
from the upstream clock but with an independent output divider
(see the page on the digital locked loop). The core clock can
be copied to GPIO 14, and the secondary clock can be copied to
GPIO 15 for monitoring. Note that the GPIOs have a bandwidth
limit of 60MHz, and it is possible to run a clock up to about
150MHz. Frequencies higher than 60MHz will be severely
attenuated, although it should be possible to measure them
with a frequency counter.
**Trap monitoring**:
For management SoC architectures that generate a trap or fault
signal when the CPU fails, the signal can be routed to GPIO 13
for monitoring.
**IRQ source**:
GPIO pads 7 and 12 can be set to be the source for two IRQ lines
into the management SoC. The specific IRQs used by the management
SoC depends largely on the SoC implementation.
**User flash SPI**:
GPIO pads 8 to 11 can be used with an alternate pass-through
programming mode if connected to an SPI flash with the pin
assignments shown above. It is recommended that any user project
that has its own SPI flash controller should use these pins, so
that the flash can be programmed directly from a host computer
through the housekeeping SPI interface. Since the pass-through
mode does not use QSPI mode, only four pins are needed for the
pass-through function. If the user project's SPI flash controller
supports quad mode, then the additional two data pins can use
any available GPIO. There is no requirement for the user to
make use of these pins for an SPI flash, but the pass-through
mode is implemented on these pins as a convenience. To use the
pass-through mode, the following must be done:
1. The GPIO pads 8 to 11 are put under management SoC control with the "management enable" bit.
2. The housekeeping SPI pads 1 to 4 must be under management SoC control.
3. The houskeeping SPI is enabled.
4. The housekeeping SPI is given the command to enter pass-through mode.
In theory, any pins can be set to management control through the
housekeeping SPI and bit-banged, but the dedicated pass-through
mode is much faster and easier to implement since the SPI commands
can be passed straight through a USB connection from a host
computer.
*As noted above*, some of the special functions are enabled per implementation
of the management SoC (``debug``, ``UART``, ``SPI master``, ``flash QSPI``). For the
register setting that enable these functions, please see the documentation
for the management SoC. The enables are specified to be placed at the
following locations (but the actual location may be implementation dependent):
.. code:: bash
UART: 0x20000008 bit 0 = UART enable
SPI master: 0x24000000 bit 13 = SPI master enable
QSPI: 0x2d000000 bit 21 = QSPI enable
The remaining special functions are controlled by the housekeeping module,
and **the special function enables are registered as shown below**:
- Register name = ``reg_hkspi_disable``
- Memory location = ``0x26200010``
- Housekeeping SPI location = ``0x1c``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x1c | | | | | | | |house- |
| | | | | | | | |keeping|
| | | | | | | | |disable|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: Housekeeping SPI disable
- value 0 = Housekeeping SPI is enabled on GPIO pins 1 to 4
- value 1 = Housekeeping SPI is disabled; GPIO pins 1 to 4 are general-purpose I/O.
--------------------------------------------------------------------------
- Register name = ``reg_trap_out_dest``, ``reg_clk_out_dest``
- Memory location = ``0x26200004``
- Housekeeping SPI location = ``0x1b``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x1b | | | | | |clk1 |clk2 |trap |
| | | | | | |monitor|monitor|monitor|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: Trap source monitor
- value = 0: GPIO pin 13 is general-purpose I/O
- value = 1: GPIO pin 13 outputs the CPU trap state, if available
*bit 1*: User clock monitor
- value = 0: GPIO pin 15 is general-purpose I/O
- value = 1: GPIO pin 15 outputs the user clock.
*bit 2*: Core clock monitor
- value = 0: GPIO pin 14 is general-purpose I/O
- value = 1: GPIO pin 14 outputs the core clock.
--------------------------------------------------------------------------
- Register name = ``reg_irq_source``
- Memory location = ``0x2620000c``
- Housekeeping SPI location = ``0x1c``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x1b | | | | | | | irq 2 | irq 1 |
| | | | | | | | source| source|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bit 0: IRQ 1 source
- value = 0: GPIO pin 7 is general-purpose I/O
- value = 1: GPIO pin 7 is an interrupt to the CPU (the interrupt number is dependent on the management SoC architecture implementation).
bit 1: IRQ 2 source
- value = 0: GPIO pin 12 is general-purpose I/O
- value = 1: GPIO pin 12 is an interrupt to the CPU (the interrupt number is dependent on the management SoC architecture implementation).

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.. raw:: html
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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# Licensed under the Apache License, Version 2.0 (the "License");
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#
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# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
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================================
GPIO pin power-on configuration
================================
The Caravel design for MPW-two includes a new feature that allows the
designer of the user project area to specify how the GPIO pins will be
configured on power-up.
For MPW-one, all user-area GPIO pins (``mprj_io[0]`` to ``mprj_io[37]``) had a
fixed configuration on power-up with management access, and an input
function on ``mprj_io[37:6]``. ``mprj_io[5:1]`` belong to the housekeeping SPI
and are configured for SPI use; ``mprj_io[0]`` is for system debug but was
unused on MPW-one. The purpose of this configuration is to keep the
chip from generating current on the outputs until after power-up. It
is the responsibility of the management SoC flash program to configure
the GPIO pins for the function needed by the user project.
**There were two issues with this configuration:**
1. The configuration of the GPIO is completely dependent on the management SoC
2. It is possible for a user project to be designed such that the user project attempts to start communicating with the outside world before the management SoC has configured the GPIO, and may end up in a stalled state before it can be configured.
To make the system more flexible, the new design allows the configuration
of the GPIOs on power-up to be custom configured. The configuration is
described in file ``user_defines.v``. A default set of definitions
corresponding to the original configuration of MPW-one is supplied with
the caravel repository in file ``verilog/rtl/user_defines.v``.
The file ``user_defines.v`` contains a set of verilog definitions in the form:
.. code:: bash
define USER_CONFIG_GPIO_<n>_INIT <value>
where ``<n>`` is the GPIO index; e.g., ``USER_CONFIG_GPIO_5`` corresponds to pin ``mprj_io[5]``. The default ``<value>`` is a 13-bit value that is the bit setting of the GPIO configuration.
Because the raw bit value is an inconvenient form, a number of additional verilog definitions have been made at the top of the file.
These definitions have the same names as those from the ``defs.h`` file included in management SoC C programs.
**These are the values most likely to be of interest to the user project designer, and are as follows:**
``GPIO_MODE_MGMT_STD_INPUT_NOPULL (13'h0403)``:
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has no pull-up or pull-down.
``GPIO_MODE_MGMT_STD_INPUT_PULLDOWN (13'h0803)``:
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-down.
``GPIO_MODE_MGMT_STD_INPUT_PULLUP (13'h0c03)``:
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-up.
``GPIO_MODE_MGMT_STD_OUTPUT (13'h1809)``:
The management SoC has access to the GPIO pin.
The pin is an output (input disbled).
``GPIO_MODE_MGMT_STD_BIDIRECTIONAL (13'h1801)``:
The management SoC has access to the GPIO pin.
The pin is either an output or an input, depending on the state
of the output enable pin. Only GPIO pins 0 (debug), 1 (housekeeping
SPI SDO), 35 (SPI master SDO), 36 (flash IO2), and 37 (flash IO3)
are able to be set as bidirectional, and the bidirectional function
is only used by the associated system function (debug, housekeeping
SPI, or SPI master).
``GPIO_MODE_MGMT_STD_ANALOG (13'h000b)``:
The management SoC has access to the GPIO pin.
All digital buffers (input and output) are turned off. There is
no effective difference between user or management control in this
case. Only user projects may supply analog signals to the GPIO
pads.
``GPIO_MODE_USER_STD_INPUT_NOPULL (13'h0402)``:
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has no pull-up or pull-down.
``GPIO_MODE_USER_STD_INPUT_PULLDOWN (13'h0802)``:
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-down.
``GPIO_MODE_USER_STD_INPUT_PULLUP (13'h0c02)``:
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-up.
``GPIO_MODE_USER_STD_OUTPUT (13'h1808)``:
The user project has access to the GPIO pin.
The pin is an output (input disbled).
``GPIO_MODE_USER_STD_BIDIRECTIONAL (13'h1800)``:
The user project has access to the GPIO pin.
The pin is bidirectional. Input is always enabled, and output
is enabled if the corresponding OEB (output-enable-bar) pin is
driven low by the user project.
``GPIO_MODE_USER_STD_OUT_MONITORED (13'h1802)``:
The user project has access to the GPIO pin.
The pin is bidirectional (see bidirectional mode, above).
The value of the pin is copied to the management SoC for
purposes of signal monitoring (i.e., the pin simultaneously
acts as mode ``MGMT_STD_INPUT_NOPULL`` as seen from the
management SoC).
``GPIO_MODE_USER_STD_ANALOG (13'h000a)``:
The user project has access to the GPIO pin.
Both input and output buffers are disabled. If the user
project connects an analog signal to this pad, it will
appear (unbuffered) on the pad.
GPIO indexes 0 to 5 are not represented in this file, because the Caravel
design requires that the debug function and the housekeeping SPI function
be accessible during initial power-on and while the management SoC is held
in reset. This allows the housekeeping to access the full chip reset and
the pass-through programming modes, so that the demonstration board cannot
be accidentally "bricked" by writing a program that both prevents the
system from working and prevents the housekeeping SPI or debug functions
from being accessed. If you want to have the user project run without setup
from the management SoC program, you will need to avoid using GPIO pins 0
to 5. If you need to use pins 0 to 5, they will have to be configured by
the management SoC program.
The default setting for all GPIO pins is ``GPIO_MODE_MGMT_STD_INPUT_NOPULL``,
corresponding to a pad that is under the control of the management SoC
and is configured as an input, with the output buffer disabled.
To set different defaults, copy the file ``user_defines.v`` to the user
project space and place it in the verilog/rtl/ directory. Then change
the definition for each of the GPIO pins to correspond to the GPIO
configuration that your project needs on startup.
The settings in ``user_defines.v`` are sufficient for verilog full-chip
simulation. The actual changes to the layout are done at time of tape-in,
when the Caravel chip is assembled. The contents of ``user_defines.v`` are
used to via-program the GPIO default block layout. The final layout and
GDS will reflect this configuration definition.

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.. raw:: html
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-->
==================================
Caravel management protect module
==================================
The management protection module sits between the management SoC and
the user project area on the Caravel chip. Its purpose is to maintain
a protective buffer between the two, so that the user project area can
be completely powered down without the management SoC dumping current
into the user project circuits.
The management protection module has two main functions:
1. Put tristate buffers on all outputs of the management SoC or
housekeeping that connect to the user project wrapper pins, enabled
with the 1/0 ("power good") state of the user project primary digital
power supply (vccd1). This ensures that if the user project vccd1
supply is not present and powered up to 1.8V, then the management SoC
and housekeeping modules cannot generate current on these pins that
would sink into the user project area.
2. AND all outputs of the user project that connect to the management
SoC with memory-mapped enable bits. This allows the user project to
leave any pins of the user project wrapper unconnected or tristated.
Unconnected outputs of the user project wrapper going to the management
SoC can be floating and will not affect operation of the chip as long
as the respective enable bits are not set in the corresponding registers.
Most of the protection circuitry is transparent to the user project, but
the input enable registers must be set by the program running on the
management SoC for the user project to be able to communicate data to the
management SoC through either the logic analyzer interface or the wishbone
bus interface.
--------------------------------------------------------------------------
- Register name = ``reg_power_good``
- Memory location = ``0x2f000000``
- Housekeeping SPI location = ``0x1a``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | | | | | user1 | user2 | user1 | user2 |
| 0x1a | | | | | vccd | vccd | vdda | vdda |
| | | | | | power | power | power | power |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: User 2 domain VDDA ``3.3V`` supply (VDDA2) power good (read-only)
- value 1 = Supply VDDA2 is present and powered (``1.8V`` to ``5.5V``)
- value 0 = Supply VDDA2 is not present or under-voltage
*bit 1*: User 1 domain VDDA ``3.3V`` supply (VDDA1) power good (read-only)
- value 0 = Supply VDDA1 is not present or under-voltage
- value 1 = Supply VDDA1 is present and powered (``1.8V`` to ``5.5V``)
*bit 2*: User 2 domain VCCD ``1.8V`` supply (VCCD2) power good (read-only)
- value 0 = Supply VCCD2 is not present or under-voltage
- value 1 = Supply VCCD2 is present and ``1.8V``
*bit 3*: User 1 domain VCCD ``1.8V`` supply (VCCD1) power good (read-only)
- value 0 = Supply VCCD1 is not present or under-voltage
- value 1 = Supply VCCD1 is present and ``1.8V``
--------------------------------------------------------------------------
- Register name = ``reg_la0_iena``
- Memory location = ``0x25000020`` to ``0x25000023`` (32 bits or 4 bytes or 1 word)
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | la | la | la | | la | la | la | la |
| | iena | iena | iena | ... | iena | iena | iena | iena |
| | [31] | [30] | [29] | | [3] | [2] | [1] | [0] |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
- Register name = ``reg_la1_iena``
- Memory location = ``0x25000024`` to ``0x25000027`` (32 bits or 4 bytes or 1 word)
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | la | la | la | | la | la | la | la |
| | iena | iena | iena | ... | iena | iena | iena | iena |
| | [63] | [62] | [61] | | [35] | [34] | [33] | [32] |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
- Register name = ``reg_la2_iena``
- Memory location = ``0x25000028`` to ``0x2500002b`` (32 bits or 4 bytes or 1 word)
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | la | la | la | | la | la | la | la |
| | iena | iena | iena | ... | iena | iena | iena | iena |
| | [95] | [94] | [93] | | [67] | [66] | [65] | [64] |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
- Register name = ``reg_la3_iena``
- Memory location = ``0x2500002c`` to ``0x2500002f`` (32 bits or 4 bytes or 1 word)
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | la | la | la | | la | la | la | la |
| | iena | iena | iena | ... | iena | iena | iena | iena |
| | [127] | [126] | [125 | | [99] | [98] | [97] | [96] |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
**Note**
The la_iena[] bits are not ports of the user project wrapper.
They originate in the management SoC and terminate at the management
protect module. They can only be set from the management SoC program.
--------------------------------------------------------------------------
- Register name = ``reg_irq_enable``
- Memory location = ``0x2f000000``
-
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | | | | | | irq 2 | irq 1 | irq 0 |
| | | | | | | enable| enable| enable|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: IRQ 0 enable
- value 0 = User IRQ 0 from the user project is disabled and may be left unconnected or tristated.
- value 1 = User IRQ 0 from the user project is enabled and must be connected and driven.
*bit 1*: IRQ 1 enable
- value 0 = User IRQ 1 from the user project is disabled and may be left unconnected or tristated.
- value 1 = User IRQ 1 from the user project is enabled and must be connected and driven.
*bit 2*: IRQ 2 enable
- value 0 = User IRQ 2 from the user project is disabled and may be left unconnected or tristated.
- value 1 = User IRQ 2 from the user project is enabled and must be connected and driven.
--------------------------------------------------------------------------
- Register name = ``reg_wb_enable``
- Memory location = ``0x2f000000``
-
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | | | | | | | | wb |
| | | | | | | | | enable|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
*bit 0*: User wishbone enable
- value 0 = Wishbone signals wbs_dat_o and wbs_ack_o are disabled and may be left unconnected.
- value 1 = Wishbone signals wbs_dat_o and wbs_ack_o are enabled and must be connected and driven.

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.. raw:: html
<!---
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-->
=========================================
Caravel memory map vs. SPI register map
=========================================
================ =========================== ============================== =======================
SPI register description signal memory map address
================ =========================== ============================== =======================
00 SPI status (reserved) (undefined) 2610_0000
01 Manufacturer ID (high) mfgr_id[11:8] 2610_0006
02 Manufacturer ID (low) mfgr_id[7:0] 2610_0005
03 Product ID prod_id[7:0] 2610_0004
04 User project ID mask_rev[31:24] 2610_000b
05 User project ID mask_rev[23:16] 2610_000a
06 User project ID mask_rev[15:8] 2610_0009
07 User project ID mask_rev[7:0] 2610_0008
08 PLL enables pll_dco_ena, pll_ena 2610_000c
09 PLL bypass pll_bypass 2610_0010
0a IRQ irq 2610_0014
0b Reset reset 2610_0018
0c CPU trap state trap 2610_0028
0d PLL trim pll_trim[31:24] 2610_001f
0e PLL trim pll_trim[23:16] 2610_001e
0f PLL trim pll_trim[15:8] 2610_001d
10 PLL trim pll_trim[7:0] 2610_001c
11 PLL source pll90_sel[2:0], pll_sel[2:0] 2610_0020
12 PLL divider pll_div[4:0] 2610_0024
13 GPIO control serial_resetn/clock/data 2600_0000
14 SRAM read-only control hkspi_sram_clk/csb 2610_0034
15 SRAM read-only address hkspi_sram_addr 2610_0030
16 SRAM read-only data hkspi_sram_data[31:24] 2610_002f
17 SRAM read-only data hkspi_sram_data[23:16] 2610_002e
18 SRAM read-only data hkspi_sram_data[15:8] 2610_002d
19 SRAM read-only data hkspi_sram_data[7:0] 2610_002c
1a Power monitor usr1/2_vcc/vdd_pwrgood 2620_0000
1b Output redirect clk1/clk2/trap_output_dest 2620_0004
1c Input redirect irq_8/7_inputsrc 2620_000c
1d GPIO[0] configure gpio_configure[0][12:8] 2600_0025
1e GPIO[0] configure gpio_configure[0][7:0] 2600_0024
1f GPIO[1] configure gpio_configure[1][12:8] 2600_0029
20 GPIO[1] configure gpio_configure[1][7:0] 2600_0028
21 GPIO[2] configure gpio_configure[2][12:8] 2600_002d
22 GPIO[2] configure gpio_configure[2][7:0] 2600_002c
23 GPIO[3] configure gpio_configure[3][12:8] 2600_0031
24 GPIO[3] configure gpio_configure[3][7:0] 2600_0030
25 GPIO[4] configure gpio_configure[4][12:8] 2600_0035
26 GPIO[4] configure gpio_configure[4][7:0] 2600_0034
27 GPIO[5] configure gpio_configure[5][12:8] 2600_0039
28 GPIO[5] configure gpio_configure[5][7:0] 2600_0038
29 GPIO[6] configure gpio_configure[6][12:8] 2600_003d
2a GPIO[6] configure gpio_configure[6][7:0] 2600_003c
2b GPIO[7] configure gpio_configure[7][12:8] 2600_0041
2c GPIO[7] configure gpio_configure[7][7:0] 2600_0040
2d GPIO[8] configure gpio_configure[8][12:8] 2600_0045
2e GPIO[8] configure gpio_configure[8][7:0] 2600_0044
2f GPIO[9] configure gpio_configure[9][12:8] 2600_0049
30 GPIO[9] configure gpio_configure[9][7:0] 2600_0048
31 GPIO[10] configure gpio_configure[10][12:8] 2600_004d
32 GPIO[10] configure gpio_configure[10][7:0] 2600_004c
33 GPIO[11] configure gpio_configure[11][12:8] 2600_0051
34 GPIO[11] configure gpio_configure[11][7:0] 2600_0050
35 GPIO[12] configure gpio_configure[12][12:8] 2600_0055
36 GPIO[12] configure gpio_configure[12][7:0] 2600_0054
37 GPIO[13] configure gpio_configure[13][12:8] 2600_0059
38 GPIO[13] configure gpio_configure[13][7:0] 2600_0058
39 GPIO[14] configure gpio_configure[14][12:8] 2600_005d
3a GPIO[14] configure gpio_configure[14][7:0] 2600_005c
3b GPIO[15] configure gpio_configure[15][12:8] 2600_0061
3c GPIO[15] configure gpio_configure[15][7:0] 2600_0060
3d GPIO[16] configure gpio_configure[16][12:8] 2600_0065
3e GPIO[16] configure gpio_configure[16][7:0] 2600_0064
3f GPIO[17] configure gpio_configure[17][12:8] 2600_0069
40 GPIO[17] configure gpio_configure[17][7:0] 2600_0068
41 GPIO[18] configure gpio_configure[18][12:8] 2600_006d
42 GPIO[18] configure gpio_configure[18][7:0] 2600_006c
43 GPIO[19] configure gpio_configure[19][12:8] 2600_0071
44 GPIO[19] configure gpio_configure[19][7:0] 2600_0070
45 GPIO[20] configure gpio_configure[20][12:8] 2600_0075
46 GPIO[20] configure gpio_configure[20][7:0] 2600_0074
47 GPIO[21] configure gpio_configure[21][12:8] 2600_0079
48 GPIO[21] configure gpio_configure[21][7:0] 2600_0078
49 GPIO[22] configure gpio_configure[22][12:8] 2600_007d
4a GPIO[22] configure gpio_configure[22][7:0] 2600_007c
4b GPIO[23] configure gpio_configure[23][12:8] 2600_0081
4c GPIO[23] configure gpio_configure[23][7:0] 2600_0080
4d GPIO[24] configure gpio_configure[24][12:8] 2600_0085
4e GPIO[24] configure gpio_configure[24][7:0] 2600_0084
4f GPIO[25] configure gpio_configure[25][12:8] 2600_0089
50 GPIO[25] configure gpio_configure[25][7:0] 2600_0088
51 GPIO[26] configure gpio_configure[26][12:8] 2600_008d
52 GPIO[26] configure gpio_configure[26][7:0] 2600_008c
53 GPIO[27] configure gpio_configure[27][12:8] 2600_0091
54 GPIO[27] configure gpio_configure[27][7:0] 2600_0090
55 GPIO[28] configure gpio_configure[28][12:8] 2600_0095
56 GPIO[28] configure gpio_configure[28][7:0] 2600_0094
57 GPIO[29] configure gpio_configure[29][12:8] 2600_0099
58 GPIO[29] configure gpio_configure[29][7:0] 2600_0098
59 GPIO[30] configure gpio_configure[30][12:8] 2600_009d
5a GPIO[30] configure gpio_configure[30][7:0] 2600_009c
5b GPIO[31] configure gpio_configure[31][12:8] 2600_00a1
5c GPIO[31] configure gpio_configure[31][7:0] 2600_00a0
5d GPIO[32] configure gpio_configure[32][12:8] 2600_00a5
5e GPIO[32] configure gpio_configure[32][7:0] 2600_00a4
5f GPIO[33] configure gpio_configure[33][12:8] 2600_00a9
60 GPIO[33] configure gpio_configure[33][7:0] 2600_00a8
61 GPIO[34] configure gpio_configure[34][12:8] 2600_00ad
62 GPIO[34] configure gpio_configure[34][7:0] 2600_00ac
63 GPIO[35] configure gpio_configure[35][12:8] 2600_00b1
64 GPIO[35] configure gpio_configure[35][7:0] 2600_00b0
65 GPIO[36] configure gpio_configure[36][12:8] 2600_00b5
66 GPIO[36] configure gpio_configure[36][7:0] 2600_00b4
67 GPIO[37] configure gpio_configure[37][12:8] 2600_00b9
68 GPIO[37] configure gpio_configure[37][7:0] 2600_00b8
69 GPIO data mgmt_gpio_in[37:32] 2600_0010
6a GPIO data mgmt_gpio_in[31:24] 2600_000f
6b GPIO data mgmt_gpio_in[23:16] 2600_000e
6c GPIO data mgmt_gpio_in[15:8] 2600_000d
6d GPIO data mgmt_gpio_in[7:0] 2600_000c
6e Power control pwr_ctrl_out[3:0] 2600_0004
6f HK SPI disable hkspi_disable 2620_0010
================ =========================== ============================== =======================

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.. raw:: html
<!---
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
-->
======================
Caravel Power control
======================
The user project power control register is a "reserved" register that is
intended for future use with on-chip LDOs to power the user project
area. In the current version of the Caravel chip, it has no function.
In the current version of the Caravel chip, all user area power supplies
are provided by voltage regulators on the demonstration/development
board.
**The usable ranges of these power supplies is**:
user1 vccd (VCCD1) = ``1.8V``
user2 vccd (VCCD2) = ``1.8V``
user1 vdda (VDDA1) = ``1.8V`` to ``5.5V`` (nominally ``3.3V``)
user2 vdda (VDDA2) = ``1.8V`` to ``5.5V`` (nominally ``3.3V``)
It is the responsibility of the user project area designer to ensure that
the value of VDDA1 and VDDA2 is compatible with the circuitry connected
to it in the user project.
--------------------------------------------------------------------------
- Register name = ``reg_mprj_pwr``
- Memory location = ``0x26000004``
- Housekeeping SPI location = ``0x6e``
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x6e | | | | | user1 | user2 | user1 | user2 |
| | | | | | vccd | vccd | vdda | vdda |
+------+-------+-------+-------+-------+-------+-------+-------+-------+