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Started a set of text documents to describe all of the register sets 

and describe the various functions of Caravel (especially housekeeping).
This should eventually be formatted to match the rest of the
documentation.
This commit is contained in:
Tim Edwards 2021-12-21 20:00:29 -05:00
parent 1c9ca7e693
commit 31e3d9c106
4 changed files with 311 additions and 2 deletions
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9
docs/other/clamp_list.txt
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@ -42,6 +42,11 @@ New overlay types created:
5. sky130_ef_io__vccd_lvc_clamped_pad: sky130_ef_io__vccd_lvc_pad + overlay (3)
6. sky130_ef_io__vssd_lvc_clamped_pad: sky130_ef_io__vssd_lvc_pad + overlay (3)
7. sky130_ef_io__vccd_lvc_clamped2_pad: sky130_ef_io__vccd_lvc_pad + overlay (4)
7. sky130_ef_io__vssd_lvc_clamped2_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
8. sky130_ef_io__vssd_lvc_clamped2_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
9. sky130_ef_io__vccd_lvc_clamped3_pad: sky130_ef_io__vccd_lvc_pad + overlay (4)
10. sky130_ef_io__vssd_lvc_clamped3_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
NOTE: The "clamped3" pads correspond to a change in the Caravel design for MPW-2,
in which the vccd/vssd domain has continuous supply rings around the chip
periphery. The pad connection of these two pads does not connect to the padframe
power rings, but connects to a separate set of power rails in the chip core.

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docs/other/digital_locked_loop.txt Normal file
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@ -0,0 +1,166 @@
Caravel digital locked loop
----------------------------------
The Caravel digital locked loop (DLL) is an all-digital clock generating
module.
The GPIO pins on Caravel have a limit of 50MHz input. Internally, it is
possible to generate a clean oscillation of up to around 200MHz or higher.
To ensure large margins of safety, the Caravel demonstration board ships
with an on-board oscillator of 10MHz. The operational frequency of the
management SoC on Caravel differs according to which management SoC
architecture is present, but is generally in the range of around 50MHz.
The DLL comprises an on-chip tunable ring oscillator and a feedback
controller for locking to a known input clock. It can operate in either
free-running (DCO) or locked (DLL) modes. The Caravel system can run
directly off of the external clock (bypass mode), the free-running DCO,
or the DLL locked to the external clock.
The DLL's tunable oscillator has an operating range of approximately
75MHz to 150MHz. The oscillator is a loop of from 13 to 39 inverter
stages with 26 bits of trim. Each trim bit adds or subtracts one of
the stages. So there are 27 effective frequency steps covering a range
of about 75MHz, with an incremental delay of about 250ps per step.
In the Caravel memory map, the DLL is controlled by a handful of registers
as shown below. These registers are in the housekeeping SPI module, and
so can be controlled either from an external source through the housekeeping
SPI, or internally through the management SoC.
WARNING: The management SoC altering its own clock has not yet been tested
as of this writing; however, the core clock should be guaranteed to be glitch-
free through transistions from external clock to DLL output and vice versa.
DLL operation
-----------------
The DLL operates by taking the ring oscillator output, reducing its frequency
through a feedback divider, and comparing the result to the input clock.
If the frequency of the divided-down ring oscillator output is faster than
the input clock frequency, then an additional delay stage is added to the
ring oscillator, making it run slower. If the frequency of the divided-down
ring oscillator output is slower than the input clock frequency, then a delay
stage is subtracted from the ring oscillator, making it faster. This
operation is performed in a continuous loop to keep the DLL frequency locked
to the input clock.
WARNING: Using discrete delay state insertion and removal results in high
phase noise (cycle to cycle jitter) on the core clock when running in DLL mode,
due to instantaneous changes of 250ps between cycles (a 0.25% change in the
clock period). User projects that require a clock with low phase noise should
use the external clock (DLL in bypass mode), and if the project requires a
higher clock rate, then the 10MHz clock on the demonstration board may be
replaced with another oscillator of the same footprint with a frequency up
to 50MHz. The DLL running in DCO mode has low cycle-to-cycle jitter but will
have a large drift component, as it is not temperature stabilized.
The DLL controls are memory-mapped to the housekeeping space, and are as
follows:
--------------------------------------------------------------------------
Register name = reg_hkspi_pll_ena
Memory location = 0x2610000c
Housekeeping SPI location = 0x08
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x09 | | | | | | | DCO | DLL |
| | | | | | | | ena | ena |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bit 1: DCO enable
value 0 = DCO disabled. DLL runs in active locking mode
value 1 = DCO enabled. DLL runs in DCO mode.
bit 0: DLL enable
value 0 = DLL disabled. DLL is disabled and the clock is stopped.
value 1 = DLL enabled. DLL is enabled and outputs a clock.
--------------------------------------------------------------------------
Register name = reg_hkspi_pll_bypass
Memory location = 0x26100010
Housekeeping SPI location = 0x09
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x09 | | | | | | | | DLL |
| | | | | | | | | bypass|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bit 0: DLL bypass
value 0 = DLL active. Core clock is derived from the DLL output.
value 1 = DLL bypassed. Core clock is derived from the external
clock source.
--------------------------------------------------------------------------
Register name = reg_hkspi_pll_trim
Memory location = 0x2610001c to 0x261001f
Housekeeping SPI location = 0x0d to 0x10
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x10 | | | | | | | trim25| trim24|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0f | trim23| trim22| trim21| trim20| trim19| trim18| trim17| trim16|
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0e | trim15| trim14| trim13| trim12| trim11| trim10| trim9 | trim8 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x0d | trim7 | trim6 | trim5 | trim4 | trim3 | trim2 | trim1 | trim0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
all bits: DLL manual trim value. This 26-bit value is applied to
the DLL when in DCO mode and directly controls the frequency
of the ring oscillator. Each '1' bit turns on one delay
stage in the oscillator.
NOTE: The phase relationship between the DLL outputs (for the core
clock and the user clock) is nominally 90 degrees when the trim
stages are balanced along the length of the oscillator, but this
phase can be altered with non-uniform delays.
--------------------------------------------------------------------------
Register name = reg_hkspi_pll_divider
Memory location = 0x26100024
Housekeeping SPI location = 0x12
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x12 | | | | div4 | div3 | div2 | div1 | div0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bits 4 to 0: Value of the DLL feedback divider. In active DLL mode,
the DLL output is divided down by this amount, and then the
trim is adjusted to make the divided value match the incoming
external clock.
For example, if the external clock is 10MHz and the divider value is
9 (div = 5'b01001), then the DLL will trim the oscillator to run at
10MHz * 9 = 90MHz. The value of (external clock frequency * divider
value) must always be within the DLL's trimmable range, or else the
DLL will saturate.
--------------------------------------------------------------------------
Register name = reg_hkspi_pll_source
Memory location = 0x26100020
Housekeeping SPI location = 0x11
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
| 0x11 | | | core2 | core1 | core0 | user2 | user1 | user0 |
+------+-------+-------+-------+-------+-------+-------+-------+-------+
bits 2 to 0: Value of the user clock output divider. The value of
the secondary clock ("user_clock") in the user project area
is derived from the zero-phase ring oscillator output divided
down by this amount. The values range from 1 (divide by 1)
to 7 (divide by 7).
bits 5 to 3: Value of the core clock output divider. The value of
the primary clock ("wb_clk_i") in the user project area
is derived from the 90-degree-phase ring oscillator output
divided down by this amount. The values range from 1 (divide
by 1) to 7 (divide by 7).

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docs/other/gpio_configuration.txt Normal file
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GPIO pin power-on configuration
-------------------------------
The Caravel design for MPW-two includes a new feature that allows the
designer of the user project area to specify how the GPIO pins will be
configured on power-up.
For MPW-one, all user-area GPIO pins (mprj_io[0] to mprj_io[37]) had a
fixed configuration on power-up with management access, and an input
function on mprj_io[37:6]. mprj_io[5:1] belong to the housekeeping SPI
and are configured for SPI use; mprj_io[0] is for system debug but was
unused on MPW-one. The purpose of this configuration is to keep the
chip from generating current on the outputs until after power-up. It
is the responsibility of the management SoC flash program to configure
the GPIO pins for the function needed by the user project.
There were two issues with this configuration: (1) The configuration of
the GPIO is completely dependent on the management SoC, and (2) it is
possible for a user project to be designed such that the user project
attempts to start communicating with the outside world before the
management SoC has configured the GPIO, and may end up in a stalled state
before it can be configured.
To make the system more flexible, the new design allows the configuration
of the GPIOs on power-up to be custom configured. The configuration is
described in file "user_defines.v". A default set of definitions
corresponding to the original configuration of MPW-one is supplied with
the caravel repository in file verilog/rtl/user_defines.v.
The file "user_defines.v" contains a set of verilog definitions in the
form:
`define USER_CONFIG_GPIO_<n>_INIT <value>
where <n> is the GPIO index; e.g., USER_CONFIG_GPIO_5 corresponds to
pin mprj_io[5]. The default <value> is a 13-bit value that is the bit
setting of the GPIO configuration. Because the raw bit value is an
inconvenient form, a number of additional verilog definitions have been
made at the top of the file. These definitions have the same names as
those from the "defs.h" file included in management SoC C programs.
These are the values most likely to be of interest to the user project
designer, and are as follows:
GPIO_MODE_MGMT_STD_INPUT_NOPULL (13'h0403):
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has no pull-up or pull-down.
GPIO_MODE_MGMT_STD_INPUT_PULLDOWN (13'h0803):
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-down.
GPIO_MODE_MGMT_STD_INPUT_PULLUP (13'h0c03):
The management SoC has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-up.
GPIO_MODE_MGMT_STD_OUTPUT (13'h1809):
The management SoC has access to the GPIO pin.
The pin is an output (input disbled).
GPIO_MODE_MGMT_STD_BIDIRECTIONAL (13'h1801):
The management SoC has access to the GPIO pin.
The pin is either an output or an input, depending on the state
of the output enable pin. Only GPIO pins 0 (debug), 1 (housekeeping
SPI SDO), 35 (SPI master SDO), 36 (flash IO2), and 37 (flash IO3)
are able to be set as bidirectional, and the bidirectional function
is only used by the associated system function (debug, housekeeping
SPI, or SPI master).
GPIO_MODE_MGMT_STD_ANALOG (13'h000b):
The management SoC has access to the GPIO pin.
All digital buffers (input and output) are turned off. There is
no effective difference between user or management control in this
case. Only user projects may supply analog signals to the GPIO
pads.
GPIO_MODE_USER_STD_INPUT_NOPULL (13'h0402):
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has no pull-up or pull-down.
GPIO_MODE_USER_STD_INPUT_PULLDOWN (13'h0802):
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-down.
GPIO_MODE_USER_STD_INPUT_PULLUP (13'h0c02):
The user project has access to the GPIO pin.
The pin is an input (output disbled) and has a 5kOhm pull-up.
GPIO_MODE_USER_STD_OUTPUT (13'h1808):
The user project has access to the GPIO pin.
The pin is an output (input disbled).
GPIO_MODE_USER_STD_BIDIRECTIONAL (13'h1800):
The user project has access to the GPIO pin.
The pin is bidirectional. Input is always enabled, and output
is enabled if the corresponding OEB (output-enable-bar) pin is
driven low by the user project.
GPIO_MODE_USER_STD_OUT_MONITORED (13'h1802):
The user project has access to the GPIO pin.
The pin is bidirectional (see bidirectional mode, above).
The value of the pin is copied to the management SoC for
purposes of signal monitoring (i.e., the pin simultaneously
acts as mode MGMT_STD_INPUT_NOPULL as seen from the
management SoC).
GPIO_MODE_USER_STD_ANALOG (13'h000a):
The user project has access to the GPIO pin.
Both input and output buffers are disabled. If the user
project connects an analog signal to this pad, it will
appear (unbuffered) on the pad.
GPIO indexes 0 to 5 are not represented in this file, because the Caravel
design requires that the debug function and the housekeeping SPI function
be accessible during initial power-on and while the management SoC is held
in reset. This allows the housekeeping to access the full chip reset and
the pass-through programming modes, so that the demonstration board cannot
be accidentally "bricked" by writing a program that both prevents the
system from working and prevents the housekeeping SPI or debug functions
from being accessed. If you want to have the user project run without setup
from the management SoC program, you will need to avoid using GPIO pins 0
to 5. If you need to use pins 0 to 5, they will have to be configured by
the management SoC program.
The default setting for all GPIO pins is "GPIO_MODE_MGMT_STD_INPUT_NOPULL",
corresponding to a pad that is under the control of the management SoC
and is configured as an input, with the output buffer disabled.
To set different defaults, copy the file "user_defines.v" to the user
project space and place it in the verilog/rtl/ directory. Then change
the definition for each of the GPIO pins to correspond to the GPIO
configuration that your project needs on startup.
The settings in "user_defines.v" are sufficient for verilog full-chip
simulation. The actual changes to the layout are done at time of tape-in,
when the Caravel chip is assembled. The contents of "user_defines.v" are
used to via-program the GPIO default block layout. The final layout and
GDS will reflect this configuration definition.

0
docs/memory_map.txt → docs/other/memory_map.txt
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