gate-level simulations from running. Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be). This is
functionally the same. Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good). Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change. This
was the only change affecting layout. Also: Revised the "pll"
testbench. This is still ongoing work. Also: Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre. Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
which is now done through setting an environment variable to point to the
location of the management SoC wrapper. Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt. Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
Tim Edwards
manarabdelaty