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caravel
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197 Commits

Author SHA1 Message Date
Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for 
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
 2021-12-03 15:06:15 -05:00
Tim Edwards 2691903104 Reworked part of the layouts of both caravel and caravan to move 
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL.  This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
 2021-12-02 20:45:39 -05:00
Tim Edwards 024801ab56 Extended the gen_gpio_defaults.py script to handle modifying the 
verilog gate-level netlists to match the correct GPIO default
value assignments, and modify the top level gate-level caravel.v
and caravan.v netlists to match.
 2021-12-02 16:04:51 -05:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
Tim Edwards 07db7f0599 Merge branch 'main' of github.com:efabless/caravel_openframe into main 
Pull before push.
 2021-12-02 14:28:00 -05:00
Tim Edwards 4cf7aa2983 Changed the synchronized reset to occur on the clock falling edge 
to give more timing margin when reset is released (note to self:
shouldn't the ext_reset also be synchronized?).
 2021-12-02 14:26:59 -05:00
manarabdelaty 85ad4b0e0f Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-02 21:20:59 +02:00
manarabdelaty c09e510017 Add target for top level sta 2021-12-02 21:20:40 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
jeffdi 78278f30d4 update make truck tcl 2021-12-02 09:28:08 -08:00
jeffdi a8730cb8ef update commit id for open_pdks 2021-12-02 08:40:05 -08:00
Tim Edwards 6482c1e011 Corrected the set_user_id.py script to (1) reverse the position of 
characters in the user_id_textblock layout, which was backwards,
and (2) add a path reference to "hexdigits" for each new character
layout encountered in the file, so that the text block layouts
are found even if "addpath hexdigits" has not been specified.
There were some other corrections to handling gzipped files that
probably does not apply in practice, where "make uncompress" has
been run prior to the set_user_id.py script.
 2021-12-02 09:35:13 -05:00
jeffdi 5896df50a8 add files for seal ring 2021-12-01 22:35:39 -08:00
jeffdi cecf6acd85 correcting magicrc file and pdkpath issues 2021-12-01 22:00:31 -08:00
jeffdi 73343aed18 correcting magicrc file and pdkpath issues 2021-12-01 21:59:03 -08:00
jeffdi aa64579d63 fix pdkpath in generate_fill.py and compositor.py 2021-12-01 21:45:48 -08:00
jeffdi 2a5589379c fix rcfile reference in generate_fill.py and compositor.py 2021-12-01 21:13:41 -08:00
jeffdi b7a4cc1d7d Merge remote-tracking branch 'origin/main' into main 2021-12-01 21:06:09 -08:00
jeffdi 547709b619 fix rcfile reference in generate_fill.py and compositor.py 2021-12-01 21:05:46 -08:00
Jeff DiCorpo de041996a6 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-01 17:27:24 -08:00
Jeff DiCorpo a2d5967b67 updating caravel.gds to final with mgmt core wrapper 2021-12-01 17:15:02 -08:00
jeffdi 2b43163b19 Merge remote-tracking branch 'origin/main' into main 2021-12-01 11:04:10 -08:00
jeffdi 0a09f3b5ac added missing scripts 2021-12-01 11:03:45 -08:00
manarabdelaty 83863fe16e Add timing log for caravel 2021-12-01 19:28:33 +02:00
Tim Edwards 0f90c813ed Added a missing route that was not completed in the previous layout 
update.  Also changed the defaults block types in the layout so that
they match the gate-level netlist.  This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
 2021-11-30 14:38:25 -05:00
Tim Edwards e0a318d2bf Fixed the GL verilog for caravel and caravan to add the two changes 
just made to the RTL verilog and layout, to separate out hk_cyc_o
and to hook up the housekeeping user_clock input.
 2021-11-30 12:31:07 -05:00
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change 
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
 2021-11-30 10:05:43 -05:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards 4c0a2303b1 Modified the GL netlists to match the layout for the GPIO defaults 
blocks;  that is, there are special versions of the block for the
first 6 GPIO pins.  That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
 2021-11-29 20:17:11 -05:00
Tim Edwards 84c97b74b2 Corrected the instance names in the layout so that they once again 
correspond to what the script gen_gpio_defaults.py is looking for.
 2021-11-29 19:57:33 -05:00
jeffdi 4fd86a58d2 testing make ship 2021-11-29 16:04:43 -08:00
jeffdi 257cb4587f testing make ship 2021-11-29 15:05:08 -08:00
jeffdi 3cf04b3e39 Merge remote-tracking branch 'origin/main' into main 2021-11-29 14:11:28 -08:00
jeffdi 41e21d2186 testing make ship 2021-11-29 14:11:12 -08:00
Tim Edwards 960a839456 Removed the read-only GDS references from the mgmt_project_hv.mag 
file, which shouldn't be there.
 2021-11-29 16:33:51 -05:00
jeffdi 36185601b7 testing make ship 2021-11-29 13:07:36 -08:00
jeffdi d20955a655 testing make ship 2021-11-29 13:03:02 -08:00
Tim Edwards cd4a052344 Made the same change to caravan as was made to caravel in the 
last commit.
 2021-11-29 14:27:02 -05:00
Tim Edwards 4dac106297 This (late and invasive) change modifies the housekeeping block to 
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i.  This
change makes it compatible with the LiteX implementation of the
wishbone bus.
 2021-11-29 14:23:30 -05:00
manarabdelaty d033d2e62d [DATA] Add spef/sdf views 2021-11-28 15:28:59 +02:00
manarabdelaty 96803bf6b2 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-28 15:06:38 +02:00
manarabdelaty d4e97b91ed Update Makefile to generate sdf file 2021-11-28 15:06:18 +02:00
jeffdi 42e2ea42d6 testing make ship 2021-11-27 16:21:01 -08:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract 
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
 2021-11-27 11:51:30 -05:00
Tim Edwards f67f7b6daf Corrected bad paths on two layouts in mag/ and most of the layouts 
in maglef/, all of which were erroneously pointing to paths in
either OpenLane or the user's home directory path.
 2021-11-26 20:00:47 -05:00
jeffdi c820dfdb40 testing make ship 2021-11-26 16:29:57 -08:00
jeffdi 91b94ad919 test gen_gpio_defaults.py 2021-11-26 15:32:13 -08:00
jeffdi fd81e0814b test gen_gpio_defaults.py 2021-11-26 15:28:03 -08:00
jeffdi b3320b7500 test gen_gpio_defaults.py 2021-11-26 14:04:00 -08:00
jeffdi 2ce03a196c test gen_gpio_defaults.py 2021-11-26 14:03:03 -08:00