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caravel/spef/gpio_control_block.spef

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[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*SPEF "ieee 1481-1999"
*DESIGN "gpio_control_block"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*1 gpio_defaults[0]
*2 gpio_defaults[10]
*3 gpio_defaults[11]
*4 gpio_defaults[12]
*5 gpio_defaults[1]
*6 gpio_defaults[2]
*7 gpio_defaults[3]
*8 gpio_defaults[4]
*9 gpio_defaults[5]
*10 gpio_defaults[6]
*11 gpio_defaults[7]
*12 gpio_defaults[8]
*13 gpio_defaults[9]
*14 mgmt_gpio_in
*15 mgmt_gpio_oeb
*16 mgmt_gpio_out
*17 one
*18 pad_gpio_ana_en
*19 pad_gpio_ana_pol
*20 pad_gpio_ana_sel
*21 pad_gpio_dm[0]
*22 pad_gpio_dm[1]
*23 pad_gpio_dm[2]
*24 pad_gpio_holdover
*25 pad_gpio_ib_mode_sel
*26 pad_gpio_in
*27 pad_gpio_inenb
*28 pad_gpio_out
*29 pad_gpio_outenb
*30 pad_gpio_slow_sel
*31 pad_gpio_vtrip_sel
*32 resetn
*33 resetn_out
*34 serial_clock
*35 serial_clock_out
*36 serial_data_in
*37 serial_data_out
*38 serial_load
*39 serial_load_out
*40 user_gpio_in
*41 user_gpio_oeb
*42 user_gpio_out
*47 zero
*48 _000_
*49 _001_
*50 _002_
*51 _003_
*52 _004_
*53 _005_
*54 _006_
*55 _007_
*56 _008_
*57 _009_
*58 _010_
*59 _011_
*60 _012_
*61 _013_
*62 _014_
*63 _015_
*64 _016_
*65 _017_
*66 _018_
*67 _019_
*68 _020_
*69 _021_
*70 _022_
*71 _023_
*72 _024_
*73 _025_
*74 _026_
*75 _027_
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*76 _042_
*77 _043_
*78 _044_
*79 _045_
*80 _046_
*81 _047_
*82 _048_
*83 _049_
*84 _050_
*85 _051_
*86 _052_
*87 _053_
*88 _054_
*89 _055_
*90 _056_
*91 _057_
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*92 _058_
*93 _059_
*94 clknet_0_serial_clock
*95 clknet_0_serial_load
*96 clknet_1_0__leaf_serial_clock
*97 clknet_1_0__leaf_serial_load
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*98 gpio_logic1
*99 gpio_outenb
*100 mgmt_ena
*101 net1
*102 net10
*103 net11
*104 net12
*105 net13
*106 net14
*107 net15
*108 net16
*109 net17
*110 net18
*111 net19
*112 net2
*113 net20
*114 net21
*115 net22
*116 net23
*117 net24
*118 net25
*119 net26
*120 net27
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*121 net28
*122 net29
*123 net3
*124 net30
*125 net31
*126 net32
*127 net33
*128 net34
*129 net35
*130 net36
*131 net37
*132 net38
*133 net39
*134 net4
*135 net40
*136 net41
*137 net42
*138 net43
*139 net44
*140 net45
*141 net46
*142 net47
*143 net48
*144 net49
*145 net5
*146 net50
*147 net51
*148 net52
*149 net53
*150 net54
*151 net55
*152 net6
*153 net7
*154 net8
*155 net9
*156 one_buffered
*157 serial_clock_out_buffered
*158 serial_load_out_buffered
*159 shift_register\[0\]
*160 shift_register\[10\]
*161 shift_register\[11\]
*162 shift_register\[12\]
*163 shift_register\[1\]
*164 shift_register\[2\]
*165 shift_register\[3\]
*166 shift_register\[4\]
*167 shift_register\[5\]
*168 shift_register\[6\]
*169 shift_register\[7\]
*170 shift_register\[8\]
*171 shift_register\[9\]
*172 zero_buffered
*173 ANTENNA__065__A0
*174 ANTENNA__066__B
*175 ANTENNA__071__B
*176 ANTENNA__072__B
*177 ANTENNA__073__A
*178 ANTENNA__073__B
*179 ANTENNA__074__A_N
*180 ANTENNA__074__B
*181 ANTENNA__075__B
*182 ANTENNA__076__B
*183 ANTENNA__077__B
*184 ANTENNA__078__B
*185 ANTENNA__079__A
*186 ANTENNA__079__B
*187 ANTENNA__080__A_N
*188 ANTENNA__080__B
*189 ANTENNA__081__B
*190 ANTENNA__082__B
*191 ANTENNA__083__A
*192 ANTENNA__083__B
*193 ANTENNA__084__A_N
*194 ANTENNA__084__B
*195 ANTENNA__085__B
*196 ANTENNA__086__B
*197 ANTENNA__087__B
*198 ANTENNA__088__B
*199 ANTENNA__089__B
*200 ANTENNA__090__B
*201 ANTENNA__091__B
*202 ANTENNA__092__B
*203 ANTENNA__093__B
*204 ANTENNA__094__B
*205 ANTENNA__095__B
*206 ANTENNA__096__B
*207 ANTENNA__125__RESET_B
*208 ANTENNA_clkbuf_0_serial_clock_A
*209 ANTENNA_clkbuf_0_serial_load_A
*210 ANTENNA_input1_A
*211 ANTENNA_input2_A
*212 ANTENNA_input3_A
*213 ANTENNA_input4_A
*214 ANTENNA_input5_A
*215 FILLER_0_3
*216 FILLER_0_31
*217 FILLER_0_57
*218 FILLER_0_91
*219 FILLER_10_85
*220 FILLER_14_98
*221 FILLER_17_98
*222 FILLER_19_55
*223 FILLER_19_70
*224 FILLER_1_32
*225 FILLER_1_98
*226 FILLER_20_98
*227 FILLER_2_42
*228 FILLER_2_48
*229 FILLER_2_52
*230 FILLER_3_48
*231 FILLER_3_80
*232 FILLER_5_56
*233 FILLER_5_98
*234 FILLER_7_98
*235 FILLER_8_52
*236 FILLER_8_98
*237 PHY_0
*238 PHY_1
*239 PHY_10
*240 PHY_11
*241 PHY_12
*242 PHY_13
*243 PHY_14
*244 PHY_15
*245 PHY_16
*246 PHY_17
*247 PHY_18
*248 PHY_19
*249 PHY_2
*250 PHY_20
*251 PHY_21
*252 PHY_22
*253 PHY_23
*254 PHY_24
*255 PHY_25
*256 PHY_26
*257 PHY_27
*258 PHY_28
*259 PHY_29
*260 PHY_3
*261 PHY_30
*262 PHY_31
*263 PHY_32
*264 PHY_33
*265 PHY_34
*266 PHY_35
*267 PHY_36
*268 PHY_37
*269 PHY_38
*270 PHY_39
*271 PHY_4
*272 PHY_40
*273 PHY_41
*274 PHY_5
*275 PHY_6
*276 PHY_7
*277 PHY_8
*278 PHY_9
*279 TAP_42
*280 TAP_43
*281 TAP_44
*282 TAP_45
*283 TAP_46
*284 TAP_47
*285 TAP_48
*286 TAP_49
*287 TAP_50
*288 TAP_51
*289 TAP_52
*290 TAP_53
*291 TAP_54
*292 TAP_55
*293 TAP_56
*294 TAP_57
*295 TAP_58
*296 TAP_59
*297 TAP_60
*298 TAP_61
*299 TAP_62
*300 TAP_63
*301 TAP_64
*302 TAP_65
*303 TAP_66
*304 TAP_67
*305 TAP_68
*306 TAP_69
*307 TAP_70
*308 TAP_71
*309 TAP_72
*310 TAP_73
*311 _060_
*312 _061__1
*313 _062__14
*314 _063_
*315 _064_
*316 _065_
*317 _066_
*318 _067_
*319 _068_
*320 _069_
*321 _070_
*322 _071_
*323 _072_
*324 _073_
*325 _074_
*326 _075_
*327 _076_
*328 _077_
*329 _078_
*330 _079_
*331 _080_
*332 _081_
*333 _082_
*334 _083_
*335 _084_
*336 _085_
*337 _086_
*338 _087_
*339 _088_
*340 _089_
*341 _090_
*342 _091_
*343 _092_
*344 _093_
*345 _094_
*346 _095_
*347 _096_
*348 _097__2
*349 _098__3
*350 _099__4
*351 _100__5
*352 _101__6
*353 _102__7
*354 _103__8
*355 _104__9
*356 _105__10
*357 _106__11
*358 _107__12
*359 _108__13
*360 _109_
*361 _110_
*362 _111_
*363 _112_
*364 _113_
*365 _114_
*366 _115_
*367 _116_
*368 _117_
*369 _118_
*370 _119_
*371 _120_
*372 _121_
*373 _122_
*374 _123_
*375 _124_
*376 _125_
*377 _126_
*378 _127_
*379 _128_
*380 _129_
*381 _130_
*382 _131_
*383 _132_
*384 _133_
*385 _134_
*386 _135_
*387 _136_
*388 _139_
*389 clkbuf_0_serial_clock
*390 clkbuf_0_serial_load
*391 clkbuf_1_0__f_serial_clock
*392 clkbuf_1_0__f_serial_load
*393 clkbuf_1_1__f_serial_clock
*394 clkbuf_1_1__f_serial_load
*395 const_source
*396 fanout21
*397 fanout22
*398 fanout23
*399 fanout24
*400 fanout25
*401 fanout26
*402 fanout27
*403 fanout28
*404 gpio_in_buf
*405 gpio_logic_high
*406 hold1
*407 hold10
*408 hold11
*409 hold12
*410 hold13
*411 hold2
*412 hold3
*413 hold4
*414 hold5
*415 hold6
*416 hold7
*417 hold8
*418 hold9
*419 input1
*420 input2
*421 input3
*422 input4
*423 input5
*424 one_buffer
*425 output10
*426 output11
*427 output12
*428 output13
*429 output14
*430 output15
*431 output16
*432 output17
*433 output18
*434 output19
*435 output20
*436 output6
*437 output7
*438 output8
*439 output9
*440 serial_clock_out_buffer
*441 serial_load_out_buffer
*442 zero_buffer
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*PORTS
gpio_defaults[0] I
gpio_defaults[10] I
gpio_defaults[11] I
gpio_defaults[12] I
gpio_defaults[1] I
gpio_defaults[2] I
gpio_defaults[3] I
gpio_defaults[4] I
gpio_defaults[5] I
gpio_defaults[6] I
gpio_defaults[7] I
gpio_defaults[8] I
gpio_defaults[9] I
mgmt_gpio_in O
mgmt_gpio_oeb I
mgmt_gpio_out I
one O
pad_gpio_ana_en O
pad_gpio_ana_pol O
pad_gpio_ana_sel O
pad_gpio_dm[0] O
pad_gpio_dm[1] O
pad_gpio_dm[2] O
pad_gpio_holdover O
pad_gpio_ib_mode_sel O
pad_gpio_in I
pad_gpio_inenb O
pad_gpio_out O
pad_gpio_outenb O
pad_gpio_slow_sel O
pad_gpio_vtrip_sel O
resetn I
resetn_out O
serial_clock I
serial_clock_out O
serial_data_in I
serial_data_out O
serial_load I
serial_load_out O
user_gpio_in O
user_gpio_oeb I
user_gpio_out I
zero O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *1 0.019232
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[0] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *176:DIODE I *D sky130_fd_sc_hd__diode_2
*I *323:B I *D sky130_fd_sc_hd__nand2b_2
*I *322:B I *D sky130_fd_sc_hd__or2_0
*I *175:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 gpio_defaults[0] 0.000428777
2 *176:DIODE 0.00163972
3 *323:B 1.4129e-05
4 *322:B 0.000142334
5 *175:DIODE 0.00021296
6 *1:45 0.00462723
7 *1:23 0.00471963
8 *1:5 0.00224565
9 *175:DIODE *116:48 3.70431e-05
10 *176:DIODE pad_gpio_dm[1] 7.09841e-05
11 *176:DIODE pad_gpio_out 7.13972e-05
12 *176:DIODE *315:A 6.08467e-05
13 *176:DIODE *315:B 3.38594e-05
14 *176:DIODE *316:A1 3.49685e-05
15 *176:DIODE *367:RESET_B 0.000142069
16 *176:DIODE *425:A 3.02163e-05
17 *176:DIODE *42:28 3.84567e-05
18 *176:DIODE *78:22 4.87242e-05
19 *176:DIODE *120:52 3.99086e-06
20 *322:B *360:RESET_B 0
21 *322:B *412:A 6.71638e-05
22 *322:B *427:A 7.02839e-06
23 *323:B *106:29 1.91246e-05
24 *1:5 *5:16 0
25 *1:5 *116:48 0.000179614
26 *1:23 serial_data_out 0.000208528
27 *1:23 *373:CLK 1.66771e-05
28 *1:23 *435:A 0.000803004
29 *1:23 *8:11 7.64213e-06
30 *1:23 *38:8 0.00200886
31 *1:23 *116:15 0.00034853
32 *1:23 *126:10 0.000131351
33 *1:45 pad_gpio_dm[1] 8.87803e-06
34 *1:45 *322:A 0
35 *1:45 *360:SET_B 0
36 *1:45 *368:CLK_N 4.34701e-05
37 *1:45 *385:D 0
38 *1:45 *12:18 1.93857e-05
39 *1:45 *13:28 6.21462e-05
40 *1:45 *38:8 0.000371112
41 *1:45 *116:15 0.000326505
*RES
1 gpio_defaults[0] *1:5 8.10714
2 *1:5 *175:DIODE 16.4964
3 *1:5 *1:23 26.6866
4 *1:23 *322:B 19.9154
5 *1:23 *1:45 23.0433
6 *1:45 *323:B 17.4868
7 *1:45 *176:DIODE 28.815
*END
*D_NET *2 0.0178764
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[10] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *336:B I *D sky130_fd_sc_hd__or2_0
*I *195:DIODE I *D sky130_fd_sc_hd__diode_2
*I *196:DIODE I *D sky130_fd_sc_hd__diode_2
*I *337:B I *D sky130_fd_sc_hd__nand2b_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 gpio_defaults[10] 0.00246996
2 *336:B 0
3 *195:DIODE 0.000648536
4 *196:DIODE 0
5 *337:B 0
6 *2:38 0.0016853
7 *2:26 0.00113193
8 *2:21 0.00256513
9 *195:DIODE *198:DIODE 0.000317503
10 *195:DIODE *210:DIODE 0.00106747
11 *195:DIODE *212:DIODE 6.27718e-05
12 *195:DIODE *311:A 0.000114271
13 *195:DIODE *320:A1 0.00012136
14 *195:DIODE *442:A 0.000606218
15 *195:DIODE *18:5 0.000191084
16 *195:DIODE *120:52 2.86829e-05
17 *2:21 pad_gpio_vtrip_sel 7.78727e-05
18 *2:21 resetn_out 0.000142113
19 *2:21 *189:DIODE 0.000243019
20 *2:21 *364:RESET_B 0.00036264
21 *2:21 *365:RESET_B 0.0001045
22 *2:21 *373:RESET_B 5.79479e-06
23 *2:21 *3:5 0
24 *2:21 *8:39 2.99671e-05
25 *2:21 *12:18 4.57907e-05
26 *2:21 *13:9 0
27 *2:21 *13:45 3.41229e-05
28 *2:21 *13:66 0.000545875
29 *2:21 *54:16 0.000455566
30 *2:21 *102:16 0.000583342
31 *2:21 *114:8 0.000219995
32 *2:21 *114:15 0.000144753
33 *2:21 *132:6 0.000361808
34 *2:21 *145:28 0.00015409
35 *2:26 *13:66 6.27718e-05
36 *2:26 *120:32 0.000154145
37 *2:26 *120:52 9.52298e-05
38 *2:38 pad_gpio_ana_pol 0
39 *2:38 *36:8 0.000256285
40 *2:38 *101:8 0.000485585
41 *2:38 *118:8 0.000300318
42 *2:38 *118:19 0.00116145
43 *2:38 *120:52 0.00083912
*RES
1 gpio_defaults[10] *2:21 40.9824
2 *2:21 *337:B 9.3
3 *2:21 *2:26 2.17857
4 *2:26 *196:DIODE 9.3
5 *2:26 *2:38 37.7679
6 *2:38 *195:DIODE 38.3
7 *2:38 *336:B 9.3
*END
*D_NET *3 0.0180651
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[11] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *338:B I *D sky130_fd_sc_hd__or2_0
*I *339:B I *D sky130_fd_sc_hd__nand2b_2
*I *197:DIODE I *D sky130_fd_sc_hd__diode_2
*I *198:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 gpio_defaults[11] 5.43606e-05
2 *338:B 0.00156791
3 *339:B 0.000575154
4 *197:DIODE 8.47319e-05
5 *198:DIODE 0.000938231
6 *3:33 0.00139749
7 *3:27 0.00141064
8 *3:22 0.00224128
9 *3:5 0.0034026
10 *197:DIODE *214:DIODE 1.87146e-05
11 *198:DIODE *436:A 6.46815e-05
12 *198:DIODE *438:A 2.39545e-05
13 *198:DIODE *442:A 0.000318331
14 *338:B *42:10 0.000118002
15 *339:B *339:A_N 9.9774e-06
16 *339:B *401:A 2.52984e-05
17 *339:B *436:A 0.000157107
18 *339:B *35:13 1.35773e-05
19 *339:B *67:10 6.36477e-05
20 *339:B *119:29 0.00113671
21 *3:5 *4:9 0
22 *3:22 *360:SET_B 0.00073007
23 *3:22 *363:CLK_N 0.000304129
24 *3:22 *372:SET_B 8.70662e-06
25 *3:22 *374:D 0.00013408
26 *3:22 *376:RESET_B 0.000340811
27 *3:22 *383:D 0.000158244
28 *3:22 *411:A 0.000282925
29 *3:22 *4:9 0
30 *3:22 *4:21 6.39653e-05
31 *3:22 *32:43 5.88253e-05
32 *3:22 *116:25 0
33 *3:22 *132:6 8.70662e-06
34 *3:22 *140:8 0.000167294
35 *3:22 *145:28 0.000206598
36 *3:22 *157:31 5.65111e-05
37 *3:22 *157:40 6.7262e-05
38 *3:27 *371:RESET_B 0.000404483
39 *3:27 *388:TE_B 6.84074e-06
40 *3:27 *428:A 6.96741e-05
41 *3:27 *438:A 0.00032603
42 *3:27 *4:21 0.000444524
43 *3:33 *438:A 0.000285475
44 *195:DIODE *198:DIODE 0.000317503
45 *2:21 *3:5 0
*RES
1 gpio_defaults[11] *3:5 1.125
2 *3:5 *3:22 48.022
3 *3:22 *3:27 11.8661
4 *3:27 *3:33 7.26786
5 *3:33 *198:DIODE 32.0321
6 *3:33 *197:DIODE 14.7464
7 *3:27 *339:B 25.8536
8 *3:5 *338:B 40.175
*END
*D_NET *4 0.0138075
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[12] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *340:B I *D sky130_fd_sc_hd__or2_0
*I *341:B I *D sky130_fd_sc_hd__nand2b_2
*I *199:DIODE I *D sky130_fd_sc_hd__diode_2
*I *200:DIODE I *D sky130_fd_sc_hd__diode_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 gpio_defaults[12] 0.000575814
2 *340:B 0.00122787
3 *341:B 0.000478138
4 *199:DIODE 0
5 *200:DIODE 1.50285e-05
6 *4:22 0.000279217
7 *4:21 0.00215326
8 *4:9 0.00321461
9 *200:DIODE *185:DIODE 0.000114271
10 *200:DIODE *186:DIODE 5.31465e-05
11 *340:B *182:DIODE 0.000118017
12 *340:B *326:A 0.000227378
13 *340:B *329:B 0.000107496
14 *340:B *385:CLK 5.04829e-06
15 *340:B *42:10 0.000118017
16 *340:B *106:13 2.12436e-05
17 *340:B *118:41 0.000265786
18 *341:B pad_gpio_dm[0] 0.000164686
19 *341:B *400:A 0.000117376
20 *341:B *439:A 0.000111352
21 *4:9 *376:RESET_B 0.000207134
22 *4:9 *427:A 7.43121e-05
23 *4:9 *116:25 0.000388109
24 *4:9 *116:39 5.33048e-05
25 *4:9 *164:16 0.000309515
26 *4:21 pad_gpio_dm[1] 0.000107844
27 *4:21 *371:RESET_B 1.42851e-05
28 *4:21 *376:RESET_B 8.18541e-05
29 *4:21 *403:A 0.000143295
30 *4:21 *409:A 0.000319562
31 *4:21 *427:A 0.00132771
32 *4:21 *436:A 0.000161626
33 *4:21 *438:A 0.000313144
34 *4:21 *158:70 0.000248457
35 *4:22 *185:DIODE 0.000151001
36 *4:22 *186:DIODE 3.00829e-05
37 *3:5 *4:9 0
38 *3:22 *4:9 0
39 *3:22 *4:21 6.39653e-05
40 *3:27 *4:21 0.000444524
*RES
1 gpio_defaults[12] *4:9 12.4107
2 *4:9 *4:21 39.5536
3 *4:21 *4:22 4.64286
4 *4:22 *200:DIODE 10.2464
5 *4:22 *199:DIODE 9.3
6 *4:21 *341:B 19.0143
7 *4:9 *340:B 37.7107
*END
*D_NET *5 0.0114954
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[1] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *335:B I *D sky130_fd_sc_hd__nand2b_2
*I *194:DIODE I *D sky130_fd_sc_hd__diode_2
*I *192:DIODE I *D sky130_fd_sc_hd__diode_2
*I *334:B I *D sky130_fd_sc_hd__or2_0
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 gpio_defaults[1] 0.000648378
2 *335:B 0
3 *194:DIODE 0
4 *192:DIODE 8.54853e-05
5 *334:B 0
6 *5:33 0.00019102
7 *5:29 0.00167321
8 *5:16 0.00221606
9 *192:DIODE *61:11 7.94337e-06
10 *5:16 *324:B 0.000160942
11 *5:16 *389:A 4.88095e-05
12 *5:16 *6:7 0
13 *5:16 *6:19 0.000196447
14 *5:16 *7:11 4.4426e-06
15 *5:16 *94:8 6.27782e-05
16 *5:16 *116:43 0.000621616
17 *5:16 *116:48 3.52873e-06
18 *5:29 *204:DIODE 0.000832864
19 *5:29 *313:A 0.00121064
20 *5:29 *364:D 1.36494e-05
21 *5:29 *365:CLK_N 7.5848e-05
22 *5:29 *371:CLK_N 0.000462422
23 *5:29 *376:D 0.000689683
24 *5:29 *377:D 7.53109e-05
25 *5:29 *389:A 1.65872e-05
26 *5:29 *440:A 1.75024e-05
27 *5:29 *9:14 0.00131296
28 *5:29 *10:7 3.10514e-05
29 *5:29 *10:20 0.000306455
30 *5:29 *96:19 0.000346414
31 *5:29 *116:43 6.08467e-05
32 *5:29 *141:16 8.50222e-05
33 *5:29 *143:10 2.75989e-05
34 *5:33 *313:A 9.89388e-06
35 *1:5 *5:16 0
*RES
1 gpio_defaults[1] *5:16 18.5357
2 *5:16 *334:B 9.3
3 *5:16 *5:29 49.5357
4 *5:29 *5:33 6.14286
5 *5:33 *192:DIODE 10.2464
6 *5:33 *194:DIODE 9.3
7 *5:29 *335:B 13.8
*END
*D_NET *6 0.00856797
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[2] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *180:DIODE I *D sky130_fd_sc_hd__diode_2
*I *178:DIODE I *D sky130_fd_sc_hd__diode_2
*I *325:B I *D sky130_fd_sc_hd__nand2b_2
*I *324:B I *D sky130_fd_sc_hd__or2_0
*CAP
1 gpio_defaults[2] 0.000155115
2 *180:DIODE 7.65937e-05
3 *178:DIODE 0
4 *325:B 2.4116e-05
5 *324:B 2.75385e-05
6 *6:36 9.6125e-05
7 *6:28 0.000919262
8 *6:19 0.00245097
9 *6:7 0.001758
10 *180:DIODE *53:10 0.000358585
11 *180:DIODE *114:55 0.00010462
12 *324:B *116:43 0.00015901
13 *325:B *116:65 0
14 *325:B *116:69 0
15 *6:7 *7:7 0
16 *6:7 *7:11 7.40248e-05
17 *6:19 serial_data_out 2.75652e-05
18 *6:19 *378:RESET_B 0.000185126
19 *6:19 *391:A 0.000122114
20 *6:19 *9:35 2.67514e-05
21 *6:19 *94:8 0.000673015
22 *6:19 *114:83 0.000113295
23 *6:19 *116:43 0.000209636
24 *6:19 *142:10 0.000133034
25 *6:28 *333:B 0.000111189
26 *6:28 *53:10 6.64392e-05
27 *6:28 *114:55 8.57749e-05
28 *6:28 *116:65 1.63255e-05
29 *6:36 *53:10 0.000167438
30 *6:36 *114:55 6.89158e-05
31 *5:16 *324:B 0.000160942
32 *5:16 *6:7 0
33 *5:16 *6:19 0.000196447
*RES
1 gpio_defaults[2] *6:7 7.44643
2 *6:7 *324:B 10.6571
3 *6:7 *6:19 38.8036
4 *6:19 *6:28 23.0357
5 *6:28 *325:B 9.72857
6 *6:28 *6:36 1.35714
7 *6:36 *178:DIODE 9.3
8 *6:36 *180:DIODE 12.3
*END
*D_NET *7 0.0138122
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[3] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *330:B I *D sky130_fd_sc_hd__or2_0
*I *331:B I *D sky130_fd_sc_hd__nand2b_2
*I *186:DIODE I *D sky130_fd_sc_hd__diode_2
*I *188:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 gpio_defaults[3] 0.000118061
2 *330:B 0.00139983
3 *331:B 0
4 *186:DIODE 0.00070585
5 *188:DIODE 0.000278787
6 *7:19 0.002539
7 *7:11 0.00237341
8 *7:7 0.00233694
9 *186:DIODE *185:DIODE 1.00901e-05
10 *186:DIODE *440:A 0.000163168
11 *186:DIODE *34:21 2.29454e-05
12 *186:DIODE *35:10 0.000219249
13 *188:DIODE *8:19 0.000205897
14 *188:DIODE *61:11 8.85947e-05
15 *330:B *33:18 2.42295e-05
16 *330:B *116:39 0.00124986
17 *330:B *116:43 0.000348103
18 *7:7 *8:11 0
19 *7:11 *414:A 0.000138453
20 *7:11 *435:A 6.00269e-05
21 *7:11 *94:8 0.000189637
22 *7:11 *116:43 0.000134717
23 *7:11 *129:15 0.000115134
24 *7:19 *206:DIODE 2.41274e-06
25 *7:19 *391:A 8.06761e-05
26 *7:19 *8:19 0.000372106
27 *7:19 *94:8 0.000205148
28 *7:19 *98:17 5.37732e-05
29 *7:19 *129:15 0.000214397
30 *200:DIODE *186:DIODE 5.31465e-05
31 *4:22 *186:DIODE 3.00829e-05
32 *5:16 *7:11 4.4426e-06
33 *6:7 *7:7 0
34 *6:7 *7:11 7.40248e-05
*RES
1 gpio_defaults[3] *7:7 6.53571
2 *7:7 *7:11 20.2679
3 *7:11 *7:19 43.5536
4 *7:19 *188:DIODE 20.8536
5 *7:19 *186:DIODE 26.6571
6 *7:11 *331:B 13.8
7 *7:7 *330:B 27.4071
*END
*D_NET *8 0.017071
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[4] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *189:DIODE I *D sky130_fd_sc_hd__diode_2
*I *332:B I *D sky130_fd_sc_hd__or2_0
*I *190:DIODE I *D sky130_fd_sc_hd__diode_2
*I *333:B I *D sky130_fd_sc_hd__nand2b_2
*CAP
1 gpio_defaults[4] 0.000894922
2 *189:DIODE 0.00130646
3 *332:B 3.3247e-05
4 *190:DIODE 7.37292e-05
5 *333:B 0.000464135
6 *8:39 0.00248778
7 *8:19 0.00183391
8 *8:11 0.00333905
9 *189:DIODE resetn_out 4.9866e-05
10 *189:DIODE *317:A_N 2.16355e-05
11 *189:DIODE *12:18 0.000445824
12 *189:DIODE *13:45 1.66771e-05
13 *189:DIODE *34:16 0.000653678
14 *189:DIODE *42:28 5.04829e-06
15 *189:DIODE *102:16 2.02035e-05
16 *190:DIODE *53:10 9.72686e-05
17 *332:B *326:A 2.16355e-05
18 *332:B *376:RESET_B 6.08467e-05
19 *332:B *396:A 1.66626e-05
20 *332:B *132:6 1.66626e-05
21 *333:B *53:10 0.000317553
22 *333:B *61:11 8.61152e-06
23 *333:B *114:55 3.98081e-06
24 *333:B *116:65 6.46815e-05
25 *333:B *116:69 2.52287e-06
26 *8:11 *373:CLK 4.64001e-05
27 *8:11 *375:CLK 5.49769e-05
28 *8:11 *386:RESET_B 0.000749588
29 *8:11 *9:14 0
30 *8:11 *96:68 7.5617e-05
31 *8:19 *201:DIODE 3.89804e-05
32 *8:19 *373:CLK 9.17798e-05
33 *8:19 *386:RESET_B 0.000914308
34 *8:19 *392:A 8.272e-05
35 *8:19 *408:A 0.000298287
36 *8:19 *9:35 0.000297142
37 *8:19 *95:8 8.02727e-05
38 *8:19 *96:68 1.48262e-05
39 *8:19 *114:55 0.000124535
40 *8:19 *116:87 0.000130755
41 *8:19 *119:29 0.000617015
42 *8:39 pad_gpio_vtrip_sel 0
43 *8:39 *183:DIODE 0.000120311
44 *8:39 *12:18 9.4191e-05
45 *8:39 *13:28 1.28301e-05
46 *188:DIODE *8:19 0.000205897
47 *1:23 *8:11 7.64213e-06
48 *2:21 *189:DIODE 0.000243019
49 *2:21 *8:39 2.99671e-05
50 *6:28 *333:B 0.000111189
51 *7:7 *8:11 0
52 *7:19 *8:19 0.000372106
*RES
1 gpio_defaults[4] *8:11 17.6696
2 *8:11 *8:19 40.6518
3 *8:19 *333:B 24.5143
4 *8:19 *190:DIODE 10.2464
5 *8:11 *8:39 5.54693
6 *8:39 *332:B 18.0225
7 *8:39 *189:DIODE 22.4509
*END
*D_NET *9 0.0147245
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[5] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *342:B I *D sky130_fd_sc_hd__or2_0
*I *202:DIODE I *D sky130_fd_sc_hd__diode_2
*I *201:DIODE I *D sky130_fd_sc_hd__diode_2
*I *343:B I *D sky130_fd_sc_hd__nand2b_2
*CAP
1 gpio_defaults[5] 0.00131569
2 *342:B 0.000429339
3 *202:DIODE 0
4 *201:DIODE 0.000401033
5 *343:B 0.000107827
6 *9:37 0.000441564
7 *9:35 0.00104205
8 *9:14 0.0019957
9 *201:DIODE *370:CLK_N 0.000936729
10 *201:DIODE *441:A 0.000205404
11 *201:DIODE *39:10 0.000216458
12 *201:DIODE *114:55 0.000218651
13 *201:DIODE *119:29 0.000132675
14 *342:B *392:A 8.36586e-06
15 *342:B *440:A 5.14448e-05
16 *342:B *14:12 2.19125e-05
17 *342:B *97:5 6.64392e-05
18 *342:B *98:17 8.29362e-05
19 *342:B *114:33 0.00063956
20 *343:B *343:A_N 0.00025527
21 *343:B *370:SET_B 1.65872e-05
22 *343:B *393:A 6.27782e-05
23 *9:14 *365:CLK_N 0.000180676
24 *9:14 *370:SET_B 0.000587064
25 *9:14 *373:CLK 0.00100289
26 *9:14 *10:7 0
27 *9:14 *96:25 0.000342667
28 *9:14 *141:16 3.39313e-06
29 *9:35 *371:CLK_N 0.000410308
30 *9:35 *378:RESET_B 2.86829e-05
31 *9:35 *386:RESET_B 0.000204112
32 *9:35 *392:A 0.000512904
33 *9:35 *114:83 0.000217447
34 *9:35 *119:29 0.000418562
35 *9:35 *158:46 0.000407526
36 *9:37 *440:A 1.13142e-05
37 *9:37 *114:55 1.03594e-05
38 *9:37 *119:29 6.23012e-05
39 *5:29 *9:14 0.00131296
40 *6:19 *9:35 2.67514e-05
41 *8:11 *9:14 0
42 *8:19 *201:DIODE 3.89804e-05
43 *8:19 *9:35 0.000297142
*RES
1 gpio_defaults[5] *9:14 37.6071
2 *9:14 *343:B 11.8893
3 *9:14 *9:35 39.9821
4 *9:35 *9:37 1.03571
5 *9:37 *201:DIODE 26.2286
6 *9:37 *202:DIODE 13.8
7 *9:35 *342:B 22.9964
*END
*D_NET *10 0.0134722
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[6] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *203:DIODE I *D sky130_fd_sc_hd__diode_2
*I *344:B I *D sky130_fd_sc_hd__or2_0
*I *345:B I *D sky130_fd_sc_hd__nand2b_2
*I *204:DIODE I *D sky130_fd_sc_hd__diode_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 gpio_defaults[6] 0.000783763
2 *203:DIODE 0
3 *344:B 0.000229227
4 *345:B 0
5 *204:DIODE 0.000479962
6 *10:44 0.00107865
7 *10:20 0.00113456
8 *10:7 0.00228779
9 *204:DIODE *313:A 6.3657e-05
10 *204:DIODE *371:CLK_N 0.000110297
11 *204:DIODE *440:A 0.000630419
12 *204:DIODE *63:10 0.000259547
13 *204:DIODE *114:55 6.0414e-05
14 *204:DIODE *114:66 7.4259e-05
15 *204:DIODE *116:91 0.000108704
16 *344:B *344:A 6.53364e-05
17 *344:B *349:A 1.99596e-06
18 *344:B *396:A 0.000200397
19 *344:B *409:A 0.000111802
20 *344:B *428:A 0.000114495
21 *344:B *132:6 0.000417827
22 *344:B *157:31 3.07796e-05
23 *10:7 *364:D 0.000227128
24 *10:7 *376:D 0.000212554
25 *10:7 *377:D 0.000103468
26 *10:7 *11:17 0.000155581
27 *10:7 *12:10 0
28 *10:7 *137:13 0.000901863
29 *10:7 *141:16 0.000181527
30 *10:20 *313:A 0.000346927
31 *10:20 *365:D 5.46907e-05
32 *10:20 *371:CLK_N 6.08467e-05
33 *10:20 *96:19 0.000351188
34 *10:20 *114:66 1.65872e-05
35 *10:20 *137:13 0.0010162
36 *10:20 *151:8 6.1664e-05
37 *10:44 *377:RESET_B 0.000106274
38 *10:44 *396:A 6.96846e-05
39 *10:44 *433:A 1.64847e-05
40 *10:44 *12:10 5.89933e-05
41 *10:44 *114:15 5.40018e-05
42 *10:44 *132:6 6.23012e-05
43 *5:29 *204:DIODE 0.000832864
44 *5:29 *10:7 3.10514e-05
45 *5:29 *10:20 0.000306455
46 *9:14 *10:7 0
*RES
1 gpio_defaults[6] *10:7 19.4821
2 *10:7 *10:20 22.875
3 *10:20 *204:DIODE 33.925
4 *10:20 *345:B 9.3
5 *10:7 *10:44 18.7857
6 *10:44 *344:B 20.7464
7 *10:44 *203:DIODE 13.8
*END
*D_NET *11 0.0155308
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[7] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *346:B I *D sky130_fd_sc_hd__or2_0
*I *347:B I *D sky130_fd_sc_hd__nand2b_2
*I *205:DIODE I *D sky130_fd_sc_hd__diode_2
*I *206:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 gpio_defaults[7] 0.00130494
2 *346:B 0
3 *347:B 1.96723e-05
4 *205:DIODE 0.000385852
5 *206:DIODE 0.00137163
6 *11:58 0.000892812
7 *11:41 0.00208611
8 *11:33 0.000648233
9 *11:17 0.00172599
10 *205:DIODE *323:A_N 1.88333e-05
11 *205:DIODE *388:TE_B 3.73474e-05
12 *205:DIODE *51:17 0.000160942
13 *205:DIODE *98:17 5.04829e-06
14 *206:DIODE *386:RESET_B 4.24488e-05
15 *206:DIODE *387:A 1.65872e-05
16 *206:DIODE *388:TE_B 0.000109884
17 *206:DIODE *111:8 1.33062e-05
18 *347:B *388:TE_B 4.76161e-06
19 *11:17 *363:CLK_N 0.000451209
20 *11:17 *364:SET_B 6.07304e-07
21 *11:17 *365:RESET_B 5.9951e-05
22 *11:17 *366:SET_B 0.000267612
23 *11:17 *376:RESET_B 0.000108543
24 *11:17 *379:RESET_B 5.04829e-06
25 *11:17 *410:A 4.9e-05
26 *11:17 *12:10 5.57954e-05
27 *11:17 *41:33 1.70006e-05
28 *11:17 *111:8 0.000906818
29 *11:17 *115:14 0.000132408
30 *11:17 *115:16 1.48211e-05
31 *11:17 *126:10 0.000103688
32 *11:17 *132:6 0.000397123
33 *11:17 *137:13 0.000734827
34 *11:17 *143:10 0.000298979
35 *11:33 *344:A 0.00025175
36 *11:33 *349:A 6.65668e-05
37 *11:33 *371:RESET_B 0.000196745
38 *11:33 *381:D 4.9e-05
39 *11:33 *428:A 0.000299984
40 *11:33 *115:14 3.49076e-06
41 *11:33 *115:16 6.4937e-05
42 *11:33 *115:20 3.20264e-05
43 *11:33 *132:6 1.18339e-05
44 *11:41 *403:A 0.000343552
45 *11:41 *97:19 0.000205476
46 *11:41 *114:27 0.000204704
47 *11:41 *115:29 0.000125322
48 *11:58 *371:RESET_B 3.54024e-05
49 *11:58 *388:TE_B 0.000694781
50 *11:58 *428:A 0.000153389
51 *11:58 *438:A 0.000113739
52 *11:58 *132:6 7.22987e-05
53 *7:19 *206:DIODE 2.41274e-06
54 *10:7 *11:17 0.000155581
*RES
1 gpio_defaults[7] *11:17 49.8304
2 *11:17 *11:33 22.4375
3 *11:33 *11:41 15.2857
4 *11:41 *206:DIODE 23.7286
5 *11:41 *11:58 18.4821
6 *11:58 *205:DIODE 13.9607
7 *11:58 *347:B 9.72857
8 *11:33 *346:B 9.3
*END
*D_NET *12 0.0127892
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[8] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *326:B I *D sky130_fd_sc_hd__or2_0
*I *182:DIODE I *D sky130_fd_sc_hd__diode_2
*I *181:DIODE I *D sky130_fd_sc_hd__diode_2
*I *327:B I *D sky130_fd_sc_hd__nand2b_2
*CAP
1 gpio_defaults[8] 0.000863251
2 *326:B 3.59006e-05
3 *182:DIODE 0.000328666
4 *181:DIODE 0.000509774
5 *327:B 4.22457e-05
6 *12:30 0.00117015
7 *12:18 0.00157053
8 *12:10 0.00209572
9 *181:DIODE *13:45 0.000268152
10 *181:DIODE *13:66 0.000298715
11 *181:DIODE *41:33 0.000152631
12 *181:DIODE *103:11 0.000556508
13 *182:DIODE *13:45 0.000126353
14 *182:DIODE *42:10 5.83017e-05
15 *182:DIODE *100:22 2.61955e-05
16 *182:DIODE *103:11 0.000418408
17 *326:B *433:A 6.54543e-05
18 *326:B *114:15 0.000142909
19 *327:B *399:A 5.84021e-05
20 *327:B *67:10 2.08648e-05
21 *12:10 *361:SET_B 0.00091077
22 *12:10 *364:SET_B 8.69298e-05
23 *12:10 *377:RESET_B 0.000257513
24 *12:10 *433:A 0.000223599
25 *12:10 *13:9 8.53124e-05
26 *12:10 *111:8 0.000389641
27 *12:10 *114:15 1.41976e-05
28 *12:18 *365:RESET_B 9.23267e-05
29 *12:18 *13:28 0.000249269
30 *12:18 *34:16 0.000139319
31 *12:18 *34:21 0
32 *12:30 *13:28 4.68315e-05
33 *12:30 *13:45 2.91684e-05
34 *12:30 *34:16 0.000617138
35 *189:DIODE *12:18 0.000445824
36 *340:B *182:DIODE 0.000118017
37 *1:45 *12:18 1.93857e-05
38 *2:21 *12:18 4.57907e-05
39 *8:39 *12:18 9.4191e-05
40 *10:7 *12:10 0
41 *10:44 *12:10 5.89933e-05
42 *11:17 *12:10 5.57954e-05
*RES
1 gpio_defaults[8] *12:10 27.3036
2 *12:10 *12:18 13.7727
3 *12:18 *327:B 18.0939
4 *12:18 *12:30 4.3218
5 *12:30 *181:DIODE 24.7732
6 *12:30 *182:DIODE 20.8982
7 *12:10 *326:B 10.6571
*END
*D_NET *13 0.0191475
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P gpio_defaults[9] I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *328:B I *D sky130_fd_sc_hd__or2_0
*I *184:DIODE I *D sky130_fd_sc_hd__diode_2
*I *329:B I *D sky130_fd_sc_hd__nand2b_2
*I *183:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 gpio_defaults[9] 0.000584375
2 *328:B 0
3 *184:DIODE 0.000350815
4 *329:B 6.43307e-05
5 *183:DIODE 0.00150037
6 *13:66 0.00173985
7 *13:45 0.00173073
8 *13:28 0.00218062
9 *13:9 0.00385934
10 *183:DIODE serial_data_out 0
11 *183:DIODE *364:CLK_N 0.000115167
12 *183:DIODE *374:RESET_B 5.58964e-05
13 *183:DIODE *414:A 0.000253345
14 *183:DIODE *38:8 4.69495e-06
15 *184:DIODE *341:A_N 0.000250197
16 *184:DIODE *439:A 0.000250343
17 *184:DIODE *145:17 0.000146158
18 *329:B *360:CLK_N 1.5714e-05
19 *329:B *33:18 1.5714e-05
20 *329:B *118:41 8.93246e-05
21 *13:9 *361:SET_B 0.000137193
22 *13:9 *366:RESET_B 0.000480081
23 *13:9 *366:SET_B 0.000205669
24 *13:9 *126:10 7.63961e-05
25 *13:28 serial_data_out 0.00021424
26 *13:45 serial_data_out 1.8472e-05
27 *13:45 *42:10 0.000186268
28 *13:45 *102:16 4.61048e-05
29 *13:66 pad_gpio_dm[1] 4.99354e-06
30 *13:66 *316:A1 0.000208834
31 *13:66 *367:SET_B 0.000445596
32 *13:66 *407:A 0.000137252
33 *13:66 *430:A 0.000140383
34 *13:66 *67:10 0.000673362
35 *13:66 *102:16 8.72115e-06
36 *13:66 *103:11 2.51664e-05
37 *13:66 *109:11 2.79483e-05
38 *13:66 *120:32 8.85135e-05
39 *13:66 *121:8 0.000435416
40 *13:66 *121:36 0.000313879
41 *181:DIODE *13:45 0.000268152
42 *181:DIODE *13:66 0.000298715
43 *182:DIODE *13:45 0.000126353
44 *189:DIODE *13:45 1.66771e-05
45 *340:B *329:B 0.000107496
46 *1:45 *13:28 6.21462e-05
47 *2:21 *13:9 0
48 *2:21 *13:45 3.41229e-05
49 *2:21 *13:66 0.000545875
50 *2:26 *13:66 6.27718e-05
51 *8:39 *183:DIODE 0.000120311
52 *8:39 *13:28 1.28301e-05
53 *12:10 *13:9 8.53124e-05
54 *12:18 *13:28 0.000249269
55 *12:30 *13:28 4.68315e-05
56 *12:30 *13:45 2.91684e-05
*RES
1 gpio_defaults[9] *13:9 17.3832
2 *13:9 *183:DIODE 25.9676
3 *13:9 *13:28 3.54223
4 *13:28 *329:B 18.8618
5 *13:28 *13:45 9.18277
6 *13:45 *13:66 43.3801
7 *13:66 *184:DIODE 22.2732
8 *13:45 *328:B 13.8
*END
*D_NET *14 0.0112184
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P mgmt_gpio_in O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *388:Z O *D sky130_fd_sc_hd__ebufn_8
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 mgmt_gpio_in 0.000310554
2 *388:Z 0.000108361
3 *14:12 0.0031934
4 *14:8 0.00299121
5 mgmt_gpio_in one 0.000470254
6 mgmt_gpio_in zero 0.000470254
7 mgmt_gpio_in *16:11 0.000446453
8 mgmt_gpio_in *18:5 0.000236302
9 *14:8 *370:SET_B 0.000328421
10 *14:8 *34:21 0.000329785
11 *14:12 one 0
12 *14:12 pad_gpio_ana_pol 0.000544517
13 *14:12 pad_gpio_dm[0] 0.000139015
14 *14:12 pad_gpio_ib_mode_sel 7.98171e-06
15 *14:12 pad_gpio_inenb 0.000389723
16 *14:12 pad_gpio_outenb 6.89449e-05
17 *14:12 *354:A 2.16355e-05
18 *14:12 *367:CLK_N 0.000236198
19 *14:12 *370:RESET_B 2.77625e-06
20 *14:12 *24:9 0.000653469
21 *14:12 *40:7 8.55407e-05
22 *14:12 *97:5 0.000127795
23 *14:12 *98:17 3.38969e-05
24 *342:B *14:12 2.19125e-05
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *388:Z *14:8 22.675
2 *14:8 *14:12 48.1161
3 *14:12 mgmt_gpio_in 5.63153
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *15 0.00668088
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P mgmt_gpio_oeb I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *419:A I *D sky130_fd_sc_hd__buf_2
*I *210:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 mgmt_gpio_oeb 0.0014428
2 *419:A 0
3 *210:DIODE 0.000889163
4 *15:8 0.00233196
5 *210:DIODE *212:DIODE 3.41139e-05
6 *210:DIODE *18:5 0.000117376
7 *15:8 one 0.000593738
8 *15:8 pad_gpio_ana_pol 0
9 *15:8 zero 0
10 *15:8 *212:DIODE 2.34686e-05
11 *15:8 *23:7 0.000180795
12 *195:DIODE *210:DIODE 0.00106747
*RES
1 mgmt_gpio_oeb *15:8 9.06841
2 *15:8 *210:DIODE 25.7286
3 *15:8 *419:A 13.8
*END
*D_NET *16 0.0109218
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P mgmt_gpio_out I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *211:DIODE I *D sky130_fd_sc_hd__diode_2
*I *420:A I *D sky130_fd_sc_hd__buf_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 mgmt_gpio_out 0.00110086
2 *211:DIODE 0.00279828
3 *420:A 5.85367e-05
4 *16:11 0.00395768
5 *211:DIODE zero 0.000207768
6 *420:A *18:5 9.92736e-05
7 *16:11 pad_gpio_ana_en 0.000448096
8 *16:11 pad_gpio_ana_sel 0.000145299
9 *16:11 *18:5 0.00165955
10 mgmt_gpio_in *16:11 0.000446453
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 mgmt_gpio_out *16:11 42.4785
2 *16:11 *420:A 11.0679
3 *16:11 *211:DIODE 49.4429
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *17 0.0065623
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
*P one O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *424:X O *D sky130_fd_sc_hd__buf_16
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 one 0.00208959
2 *424:X 0.00208959
3 one zero 0.000997543
4 one *20:9 0.000135818
5 one *36:8 0.00018576
6 mgmt_gpio_in one 0.000470254
7 *14:12 one 0
8 *15:8 one 0.000593738
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *424:X one 41.9223
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *18 0.00609629
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P pad_gpio_ana_en O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *436:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_ana_en 0.000273752
2 *436:X 0.00124876
3 *18:12 2.68684e-05
4 *18:5 0.00149565
5 pad_gpio_ana_en pad_gpio_ana_sel 7.61581e-05
6 *18:5 *174:DIODE 0.000109427
7 *18:5 *212:DIODE 6.08467e-05
8 *18:5 *311:A 5.31465e-05
9 *18:5 *36:8 0
10 mgmt_gpio_in *18:5 0.000236302
11 *195:DIODE *18:5 0.000191084
12 *210:DIODE *18:5 0.000117376
13 *420:A *18:5 9.92736e-05
14 *16:11 pad_gpio_ana_en 0.000448096
15 *16:11 *18:5 0.00165955
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *436:X *18:5 45.9786
2 *18:5 pad_gpio_ana_en 15.1689
3 pad_gpio_ana_en *18:12 0.0595333
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *19 0.00678298
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P pad_gpio_ana_pol O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *437:X O *D sky130_fd_sc_hd__buf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_ana_pol 0.00176304
2 *437:X 0.00176304
3 pad_gpio_ana_pol pad_gpio_ana_sel 4.31122e-05
4 pad_gpio_ana_pol pad_gpio_dm[0] 0.000150395
5 pad_gpio_ana_pol *367:RESET_B 1.88563e-05
6 pad_gpio_ana_pol *424:A 0.000808733
7 pad_gpio_ana_pol *20:9 3.17651e-05
8 pad_gpio_ana_pol *36:8 0.000967865
9 pad_gpio_ana_pol *101:8 0.000637172
10 pad_gpio_ana_pol *145:17 5.44807e-05
11 *2:38 pad_gpio_ana_pol 0
12 *14:12 pad_gpio_ana_pol 0.000544517
13 *15:8 pad_gpio_ana_pol 0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *437:X pad_gpio_ana_pol 44.4947
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *20 0.00763008
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
*CONN
*P pad_gpio_ana_sel O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *438:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_ana_sel 0.000995478
2 *438:X 0.00141963
3 *20:9 0.00241511
4 pad_gpio_ana_sel pad_gpio_dm[0] 3.84497e-05
5 *20:9 *214:DIODE 0.000790923
6 *20:9 *23:7 0.00130651
7 *20:9 *23:14 3.85049e-05
8 *20:9 *36:8 0.000193315
9 one *20:9 0.000135818
10 pad_gpio_ana_en pad_gpio_ana_sel 7.61581e-05
11 pad_gpio_ana_pol pad_gpio_ana_sel 4.31122e-05
12 pad_gpio_ana_pol *20:9 3.17651e-05
13 *16:11 pad_gpio_ana_sel 0.000145299
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *438:X *20:9 48.5857
2 *20:9 pad_gpio_ana_sel 36.944
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *21 0.00606828
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
*P pad_gpio_dm[0] O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *439:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_dm[0] 0.00198975
2 *439:X 0.00198975
3 pad_gpio_dm[0] pad_gpio_dm[1] 0.00047915
4 pad_gpio_dm[0] pad_gpio_ib_mode_sel 0.000144623
5 pad_gpio_dm[0] pad_gpio_inenb 0
6 pad_gpio_dm[0] *319:A_N 6.08467e-05
7 pad_gpio_dm[0] *321:A1 6.27782e-05
8 pad_gpio_dm[0] *400:A 0.000310253
9 pad_gpio_dm[0] *439:A 4.24488e-05
10 pad_gpio_dm[0] *23:7 0
11 pad_gpio_dm[0] *35:13 0.000194178
12 pad_gpio_dm[0] *118:8 0.000301947
13 pad_gpio_ana_pol pad_gpio_dm[0] 0.000150395
14 pad_gpio_ana_sel pad_gpio_dm[0] 3.84497e-05
15 *341:B pad_gpio_dm[0] 0.000164686
16 *14:12 pad_gpio_dm[0] 0.000139015
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *439:X pad_gpio_dm[0] 42.9417
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *22 0.00640973
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*P pad_gpio_dm[1] O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *425:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_dm[1] 0.00259921
2 *425:X 0.00259921
3 pad_gpio_dm[1] pad_gpio_dm[2] 7.1913e-05
4 pad_gpio_dm[1] *321:A2 2.62319e-05
5 pad_gpio_dm[1] *367:CLK_N 1.66771e-05
6 pad_gpio_dm[1] *427:A 8.06639e-05
7 pad_gpio_dm[1] *24:9 0.000178425
8 pad_gpio_dm[1] *40:7 0.000118356
9 pad_gpio_dm[1] *145:28 4.71956e-05
10 pad_gpio_dm[0] pad_gpio_dm[1] 0.00047915
11 *176:DIODE pad_gpio_dm[1] 7.09841e-05
12 *1:45 pad_gpio_dm[1] 8.87803e-06
13 *4:21 pad_gpio_dm[1] 0.000107844
14 *13:66 pad_gpio_dm[1] 4.99354e-06
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *425:X pad_gpio_dm[1] 27.4175
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *23 0.00957441
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P pad_gpio_dm[2] O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *426:X O *D sky130_fd_sc_hd__buf_16
*CAP
1 pad_gpio_dm[2] 0.00144029
2 *426:X 0.00127103
3 *23:14 0.00267487
4 *23:7 0.00250561
5 pad_gpio_dm[2] pad_gpio_holdover 4.80459e-05
6 pad_gpio_dm[2] pad_gpio_ib_mode_sel 1.66771e-05
7 pad_gpio_dm[2] user_gpio_in 2.01653e-05
8 pad_gpio_dm[2] *24:9 0
9 *23:14 *36:8 0
10 pad_gpio_dm[0] *23:7 0
11 pad_gpio_dm[1] pad_gpio_dm[2] 7.1913e-05
12 *15:8 *23:7 0.000180795
13 *20:9 *23:7 0.00130651
14 *20:9 *23:14 3.85049e-05
*RES
1 *426:X *23:7 42.3982
2 *23:7 *23:14 33.9196
3 *23:14 pad_gpio_dm[2] 34.6067
*END
*D_NET *24 0.00555131
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
*P pad_gpio_holdover O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *427:X O *D sky130_fd_sc_hd__buf_16
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_holdover 0.000142454
2 *427:X 0.000933108
3 *24:9 0.00107556
4 pad_gpio_holdover pad_gpio_ib_mode_sel 0.000361461
5 pad_gpio_holdover serial_clock_out 0.000308728
6 *24:9 pad_gpio_ib_mode_sel 0.000989575
7 *24:9 pad_gpio_outenb 0.000669036
8 *24:9 *431:A 2.99273e-05
9 *24:9 *439:A 5.35029e-05
10 *24:9 *35:13 0
11 *24:9 *40:7 0
12 *24:9 *98:17 7.54013e-05
13 *24:9 *153:10 3.26102e-05
14 pad_gpio_dm[1] *24:9 0.000178425
15 pad_gpio_dm[2] pad_gpio_holdover 4.80459e-05
16 pad_gpio_dm[2] *24:9 0
17 *14:12 *24:9 0.000653469
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *427:X *24:9 45.7286
2 *24:9 pad_gpio_holdover 12.1054
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *25 0.00545051
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P pad_gpio_ib_mode_sel O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *428:X O *D sky130_fd_sc_hd__buf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_ib_mode_sel 0.00127486
2 *428:X 0.00127486
3 pad_gpio_ib_mode_sel pad_gpio_outenb 0.000673248
4 pad_gpio_ib_mode_sel serial_clock_out 9.09671e-05
5 pad_gpio_ib_mode_sel user_gpio_in 0.000152316
6 pad_gpio_ib_mode_sel *26:8 6.33133e-05
7 pad_gpio_ib_mode_sel *35:13 0.000339778
8 pad_gpio_ib_mode_sel *98:17 6.08467e-05
9 pad_gpio_dm[0] pad_gpio_ib_mode_sel 0.000144623
10 pad_gpio_dm[2] pad_gpio_ib_mode_sel 1.66771e-05
11 pad_gpio_holdover pad_gpio_ib_mode_sel 0.000361461
12 *14:12 pad_gpio_ib_mode_sel 7.98171e-06
13 *24:9 pad_gpio_ib_mode_sel 0.000989575
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *428:X pad_gpio_ib_mode_sel 49.4953
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *26 0.00837294
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P pad_gpio_in I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *421:A I *D sky130_fd_sc_hd__buf_2
*I *212:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 pad_gpio_in 0.00145115
2 *421:A 0
3 *212:DIODE 0.000791433
4 *26:8 0.00224258
5 *212:DIODE *311:A 0.00146885
6 *212:DIODE *319:A_N 0.00078601
7 *212:DIODE *369:SET_B 7.03786e-07
8 *212:DIODE *425:A 1.65736e-05
9 *212:DIODE *42:28 0.000198655
10 *212:DIODE *102:16 3.80838e-05
11 *212:DIODE *123:8 6.09513e-05
12 *26:8 pad_gpio_inenb 0.000432312
13 *26:8 pad_gpio_out 0.000159297
14 *26:8 pad_gpio_outenb 0
15 *26:8 *316:A1 4.50545e-05
16 *26:8 *321:A1 5.76799e-05
17 *26:8 *321:A2 1.12517e-05
18 *26:8 *42:28 1.10133e-05
19 *26:8 *78:22 0.000345659
20 *26:8 *102:16 1.11698e-05
21 pad_gpio_ib_mode_sel *26:8 6.33133e-05
22 *195:DIODE *212:DIODE 6.27718e-05
23 *210:DIODE *212:DIODE 3.41139e-05
24 *15:8 *212:DIODE 2.34686e-05
25 *18:5 *212:DIODE 6.08467e-05
*RES
1 pad_gpio_in *26:8 7.63792
2 *26:8 *212:DIODE 36.3179
3 *26:8 *421:A 13.8
*END
*D_NET *27 0.00411289
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P pad_gpio_inenb O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *429:X O *D sky130_fd_sc_hd__buf_16
*CAP
1 pad_gpio_inenb 0.00144866
2 *429:X 0.00144866
3 pad_gpio_inenb pad_gpio_out 4.80459e-05
4 pad_gpio_inenb pad_gpio_outenb 0.000338897
5 pad_gpio_inenb *339:A_N 6.59359e-06
6 pad_gpio_inenb *35:13 0
7 pad_gpio_dm[0] pad_gpio_inenb 0
8 *14:12 pad_gpio_inenb 0.000389723
9 *26:8 pad_gpio_inenb 0.000432312
*RES
1 *429:X pad_gpio_inenb 39.2791
*END
*D_NET *28 0.00566097
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P pad_gpio_out O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *430:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_out 0.00133358
2 *430:X 0.00133358
3 pad_gpio_out pad_gpio_outenb 4.80459e-05
4 pad_gpio_out serial_clock_out 0.000338549
5 pad_gpio_out user_gpio_in 1.47712e-05
6 pad_gpio_out *318:B 5.11592e-05
7 pad_gpio_out *318:C 0.000391301
8 pad_gpio_out *32:30 0.00168791
9 pad_gpio_out *78:22 0.000124363
10 pad_gpio_out *123:8 5.89592e-05
11 pad_gpio_inenb pad_gpio_out 4.80459e-05
12 *176:DIODE pad_gpio_out 7.13972e-05
13 *26:8 pad_gpio_out 0.000159297
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *430:X pad_gpio_out 48.8161
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *29 0.00508433
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P pad_gpio_outenb O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *431:X O *D sky130_fd_sc_hd__buf_16
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_outenb 0.000993218
2 *431:X 0.000993218
3 pad_gpio_outenb pad_gpio_slow_sel 0.000463907
4 pad_gpio_outenb *39:16 0.000835817
5 pad_gpio_outenb *118:19 0
6 pad_gpio_ib_mode_sel pad_gpio_outenb 0.000673248
7 pad_gpio_inenb pad_gpio_outenb 0.000338897
8 pad_gpio_out pad_gpio_outenb 4.80459e-05
9 *14:12 pad_gpio_outenb 6.89449e-05
10 *24:9 pad_gpio_outenb 0.000669036
11 *26:8 pad_gpio_outenb 0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *431:X pad_gpio_outenb 38.2982
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *30 0.0069175
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P pad_gpio_slow_sel O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *432:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_slow_sel 0.000450677
2 *432:X 0.00170799
3 *30:8 0.00215867
4 pad_gpio_slow_sel pad_gpio_vtrip_sel 0.000461825
5 pad_gpio_slow_sel *41:15 0.000217808
6 *30:8 *338:A 0.000187307
7 *30:8 *413:A 0.000919373
8 *30:8 *39:16 0.00034995
9 *30:8 *118:28 0
10 pad_gpio_outenb pad_gpio_slow_sel 0.000463907
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *432:X *30:8 49.2375
2 *30:8 pad_gpio_slow_sel 5.7036
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *31 0.00920404
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P pad_gpio_vtrip_sel O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *433:X O *D sky130_fd_sc_hd__buf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 pad_gpio_vtrip_sel 0.00424575
2 *433:X 0.00424575
3 pad_gpio_vtrip_sel resetn_out 0
4 pad_gpio_vtrip_sel *209:DIODE 1.72407e-05
5 pad_gpio_vtrip_sel *32:30 6.33133e-05
6 pad_gpio_vtrip_sel *38:8 4.6634e-05
7 pad_gpio_vtrip_sel *54:16 4.56572e-05
8 pad_gpio_slow_sel pad_gpio_vtrip_sel 0.000461825
9 *2:21 pad_gpio_vtrip_sel 7.78727e-05
10 *8:39 pad_gpio_vtrip_sel 0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *433:X pad_gpio_vtrip_sel 29.1427
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *32 0.0136618
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P resetn I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *422:A I *D sky130_fd_sc_hd__buf_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*I *213:DIODE I *D sky130_fd_sc_hd__diode_2
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*CAP
1 resetn 0.00137239
2 *422:A 0
3 *213:DIODE 0.000462994
4 *32:43 0.00295657
5 *32:30 0.00386597
6 *213:DIODE *365:CLK_N 0.000254031
7 *213:DIODE *391:A 9.28161e-05
8 *213:DIODE *96:5 0.000111802
9 *213:DIODE *114:83 0.000317072
10 *32:30 resetn_out 6.33133e-05
11 *32:30 serial_clock_out 0.000280959
12 *32:30 user_gpio_in 0.000245419
13 *32:30 *318:C 8.00035e-05
14 *32:30 *320:B1 2.57465e-06
15 *32:30 *321:A1 5.48401e-05
16 *32:30 *426:A 6.08467e-05
17 *32:30 *41:15 0.000343237
18 *32:30 *102:16 9.40549e-05
19 *32:30 *103:11 8.81178e-05
20 *32:43 *347:A_N 3.54435e-05
21 *32:43 *360:SET_B 2.57465e-06
22 *32:43 *365:CLK_N 5.04829e-06
23 *32:43 *367:D 1.43229e-05
24 *32:43 *372:RESET_B 0.000207591
25 *32:43 *372:SET_B 0.000130164
26 *32:43 *380:CLK 6.08467e-05
27 *32:43 *380:D 6.08467e-05
28 *32:43 *380:RESET_B 5.37479e-05
29 *32:43 *403:A 3.35651e-05
30 *32:43 *430:A 0.000156955
31 *32:43 *96:5 0.000139947
32 *32:43 *115:29 0.000157917
33 *32:43 *153:10 4.57372e-05
34 pad_gpio_out *32:30 0.00168791
35 pad_gpio_vtrip_sel *32:30 6.33133e-05
36 *3:22 *32:43 5.88253e-05
*RES
1 resetn *32:30 46.5346
2 *32:30 *32:43 41.5179
3 *32:43 *213:DIODE 20.2464
4 *32:43 *422:A 9.3
*END
*D_NET *33 0.00816105
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P resetn_out O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *434:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 resetn_out 0.000975422
2 *434:X 0.00101224
3 *33:18 0.00198766
4 resetn_out *34:16 0.000671297
5 *33:18 *321:B1 6.00813e-05
6 *33:18 *329:A_N 0.00013147
7 *33:18 *360:CLK_N 9.87472e-05
8 *33:18 *364:RESET_B 0.000221746
9 *33:18 *413:A 0.000473045
10 *33:18 *416:A 0.000112897
11 *33:18 *42:10 0.000183821
12 *33:18 *42:28 2.44669e-05
13 *33:18 *102:16 0.000389355
14 *33:18 *109:11 0.000295379
15 *33:18 *116:15 0.000100487
16 *33:18 *116:39 2.57986e-05
17 *33:18 *141:16 0.0011019
18 pad_gpio_vtrip_sel resetn_out 0
19 *189:DIODE resetn_out 4.9866e-05
20 *329:B *33:18 1.5714e-05
21 *330:B *33:18 2.42295e-05
22 *2:21 resetn_out 0.000142113
23 *32:30 resetn_out 6.33133e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *434:X *33:18 46.4511
2 *33:18 resetn_out 3.807
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *34 0.0174746
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P serial_clock I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *389:A I *D sky130_fd_sc_hd__clkbuf_16
*I *208:DIODE I *D sky130_fd_sc_hd__diode_2
*CAP
1 serial_clock 0.00290149
2 *389:A 0.000708299
3 *208:DIODE 0
4 *34:21 0.00199284
5 *34:16 0.00560263
6 *389:A *366:RESET_B 0.000482556
7 *389:A *116:39 4.78069e-06
8 *389:A *116:43 1.1718e-05
9 *389:A *141:16 2.99747e-05
10 *34:16 serial_clock_out 4.80459e-05
11 *34:16 serial_data_out 0
12 *34:16 *322:A 8.58461e-05
13 *34:16 *323:A_N 0.000130534
14 *34:16 *361:RESET_B 5.28741e-05
15 *34:16 *364:RESET_B 0
16 *34:16 *369:CLK_N 0.000391616
17 *34:16 *369:D 9.80426e-05
18 *34:16 *384:CLK 3.76053e-05
19 *34:16 *386:D 1.56833e-05
20 *34:16 *399:A 0.000485144
21 *34:16 *117:8 2.12358e-05
22 *34:16 *162:8 1.26994e-05
23 *34:21 *364:RESET_B 0
24 *34:21 *366:RESET_B 7.84839e-05
25 *34:21 *370:SET_B 0.000229019
26 *34:21 *379:RESET_B 3.5026e-06
27 *34:21 *418:A 0.000538614
28 *34:21 *35:10 6.64392e-05
29 *34:21 *63:10 8.94038e-05
30 *34:21 *114:27 0
31 *34:21 *126:10 0.000856009
32 resetn_out *34:16 0.000671297
33 *186:DIODE *34:21 2.29454e-05
34 *189:DIODE *34:16 0.000653678
35 *5:16 *389:A 4.88095e-05
36 *5:29 *389:A 1.65872e-05
37 *12:18 *34:16 0.000139319
38 *12:18 *34:21 0
39 *12:30 *34:16 0.000617138
40 *14:8 *34:21 0.000329785
*RES
1 serial_clock *34:16 42.8484
2 *34:16 *34:21 43.9732
3 *34:21 *208:DIODE 9.3
4 *34:16 *389:A 22.8268
*END
*D_NET *35 0.0116703
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P serial_clock_out O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *440:X O *D sky130_fd_sc_hd__clkbuf_16
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_clock_out 0.00106281
2 *440:X 0.000351326
3 *35:13 0.00370719
4 *35:10 0.00299571
5 serial_clock_out serial_data_out 0
6 serial_clock_out serial_load_out 0.000416687
7 serial_clock_out user_gpio_in 0
8 serial_clock_out *41:15 0.000207339
9 *35:10 *357:A 6.84074e-06
10 *35:10 *39:10 0.000220828
11 *35:13 *320:B1 0.000196658
12 *35:13 *339:A_N 4.89072e-05
13 *35:13 *370:RESET_B 8.79845e-05
14 *35:13 *401:A 2.49791e-05
15 *35:13 *427:A 2.58616e-05
16 *35:13 *67:10 1.03403e-05
17 *35:13 *119:29 0.000144381
18 *35:13 *145:17 0.000261968
19 pad_gpio_dm[0] *35:13 0.000194178
20 pad_gpio_holdover serial_clock_out 0.000308728
21 pad_gpio_ib_mode_sel serial_clock_out 9.09671e-05
22 pad_gpio_ib_mode_sel *35:13 0.000339778
23 pad_gpio_inenb *35:13 0
24 pad_gpio_out serial_clock_out 0.000338549
25 *186:DIODE *35:10 0.000219249
26 *339:B *35:13 1.35773e-05
27 *24:9 *35:13 0
28 *32:30 serial_clock_out 0.000280959
29 *34:16 serial_clock_out 4.80459e-05
30 *34:21 *35:10 6.64392e-05
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *440:X *35:10 25.3536
2 *35:10 *35:13 42
3 *35:13 serial_clock_out 30.1232
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *36 0.0143916
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P serial_data_in I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *423:A I *D sky130_fd_sc_hd__buf_2
*I *214:DIODE I *D sky130_fd_sc_hd__diode_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_data_in 0.00186147
2 *423:A 0
3 *214:DIODE 0.00144221
4 *36:29 2.68684e-05
5 *36:8 0.00397143
6 *36:7 0.00436383
7 *214:DIODE *367:RESET_B 0.000108053
8 *214:DIODE *404:A 0.00010471
9 *36:8 *367:RESET_B 6.27718e-05
10 *36:8 *120:52 3.74005e-05
11 one *36:8 0.00018576
12 pad_gpio_ana_pol *36:8 0.000967865
13 *197:DIODE *214:DIODE 1.87146e-05
14 *2:38 *36:8 0.000256285
15 *18:5 *36:8 0
16 *20:9 *214:DIODE 0.000790923
17 *20:9 *36:8 0.000193315
18 *23:14 *36:8 0
*RES
1 serial_data_in *36:7 45.8296
2 *36:7 *36:8 56.8036
3 *36:8 *214:DIODE 37.8714
4 *36:8 *423:A 9.3
5 serial_data_in *36:29 0.0595333
*END
*D_NET *37 0.00941975
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P serial_data_out O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *435:X O *D sky130_fd_sc_hd__buf_16
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_data_out 0.00388969
2 *435:X 0.00388969
3 serial_data_out *38:8 0.000613407
4 serial_data_out *116:15 0.000558167
5 serial_clock_out serial_data_out 0
6 *183:DIODE serial_data_out 0
7 *1:23 serial_data_out 0.000208528
8 *6:19 serial_data_out 2.75652e-05
9 *13:28 serial_data_out 0.00021424
10 *13:45 serial_data_out 1.8472e-05
11 *34:16 serial_data_out 0
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *435:X serial_data_out 27.9695
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *38 0.0145347
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P serial_load I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *390:A I *D sky130_fd_sc_hd__clkbuf_16
*I *209:DIODE I *D sky130_fd_sc_hd__diode_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_load 0.00375594
2 *390:A 0
3 *209:DIODE 0.000947802
4 *38:8 0.00470374
5 *209:DIODE *386:RESET_B 5.00525e-05
6 *209:DIODE *96:25 0.000198319
7 *209:DIODE *96:34 0.000145111
8 *209:DIODE *96:41 4.94462e-05
9 *209:DIODE *97:36 0.000255038
10 *209:DIODE *114:83 0.000260325
11 *209:DIODE *158:10 8.21761e-06
12 *38:8 serial_load_out 3.84497e-05
13 *38:8 user_gpio_in 0
14 *38:8 *374:RESET_B 0.000250495
15 *38:8 *386:RESET_B 8.15182e-05
16 *38:8 *96:41 0.000101177
17 *38:8 *96:56 0.000188094
18 *38:8 *116:15 0.000285574
19 *38:8 *117:39 0.000153468
20 pad_gpio_vtrip_sel *209:DIODE 1.72407e-05
21 pad_gpio_vtrip_sel *38:8 4.6634e-05
22 serial_data_out *38:8 0.000613407
23 *183:DIODE *38:8 4.69495e-06
24 *1:23 *38:8 0.00200886
25 *1:45 *38:8 0.000371112
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_load *38:8 24.2336
2 *38:8 *209:DIODE 28.425
3 *38:8 *390:A 13.8
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *39 0.0132317
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
*P serial_load_out O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *441:X O *D sky130_fd_sc_hd__clkbuf_16
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 serial_load_out 0.00117057
2 *441:X 0.000310056
3 *39:16 0.00373391
4 *39:10 0.00287339
5 serial_load_out user_gpio_in 3.84497e-05
6 serial_load_out *41:15 0.000199406
7 *39:10 *357:A 0.000474181
8 *39:10 *441:A 6.88361e-05
9 *39:10 *97:19 0.000231952
10 *39:10 *114:27 0.00025276
11 *39:16 *371:RESET_B 5.481e-05
12 *39:16 *388:TE_B 0.00165159
13 *39:16 *40:7 9.35547e-05
14 *39:16 *118:19 0
15 pad_gpio_outenb *39:16 0.000835817
16 serial_clock_out serial_load_out 0.000416687
17 *201:DIODE *39:10 0.000216458
18 *30:8 *39:16 0.00034995
19 *35:10 *39:10 0.000220828
20 *38:8 serial_load_out 3.84497e-05
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *441:X *39:10 28.4964
2 *39:10 *39:16 49.6786
3 *39:16 serial_load_out 32.9797
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *40 0.00659257
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P user_gpio_in O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *404:Z O *D sky130_fd_sc_hd__einvp_8
*CAP
1 user_gpio_in 0.00125232
2 *404:Z 0.000826146
3 *40:7 0.00207846
4 user_gpio_in *41:15 0.00163684
5 *40:7 *388:TE_B 3.02384e-05
6 pad_gpio_dm[1] *40:7 0.000118356
7 pad_gpio_dm[2] user_gpio_in 2.01653e-05
8 pad_gpio_ib_mode_sel user_gpio_in 0.000152316
9 pad_gpio_out user_gpio_in 1.47712e-05
10 serial_clock_out user_gpio_in 0
11 serial_load_out user_gpio_in 3.84497e-05
12 *14:12 *40:7 8.55407e-05
13 *24:9 *40:7 0
14 *32:30 user_gpio_in 0.000245419
15 *38:8 user_gpio_in 0
16 *39:16 *40:7 9.35547e-05
*RES
1 *404:Z *40:7 30.3536
2 *40:7 user_gpio_in 35.143
*END
*D_NET *41 0.0129193
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P user_gpio_oeb I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *316:A0 I *D sky130_fd_sc_hd__mux2_4
*I *173:DIODE I *D sky130_fd_sc_hd__diode_2
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 user_gpio_oeb 0.0015112
2 *316:A0 0
3 *173:DIODE 0.000366353
4 *41:33 0.00210043
5 *41:15 0.00324527
6 *173:DIODE *95:8 0.000242322
7 *173:DIODE *129:15 5.27224e-05
8 *173:DIODE *158:17 0.000126335
9 *41:15 *316:S 1.65872e-05
10 *41:15 *42:10 8.4215e-05
11 *41:33 *316:S 5.481e-05
12 *41:33 *363:CLK_N 0.00012559
13 *41:33 *379:D 9.55802e-05
14 *41:33 *379:RESET_B 0.000148524
15 *41:33 *383:D 0.000299994
16 *41:33 *384:D 0
17 *41:33 *397:A 0.00018628
18 *41:33 *410:A 2.58616e-05
19 *41:33 *418:A 0.000110306
20 *41:33 *431:A 0.000396003
21 *41:33 *95:8 0.000287858
22 *41:33 *106:29 0.000141062
23 *41:33 *121:51 5.39247e-05
24 *41:33 *151:8 0.000374343
25 *41:33 *158:70 9.95234e-05
26 pad_gpio_slow_sel *41:15 0.000217808
27 serial_clock_out *41:15 0.000207339
28 serial_load_out *41:15 0.000199406
29 user_gpio_in *41:15 0.00163684
30 *181:DIODE *41:33 0.000152631
31 *11:17 *41:33 1.70006e-05
32 *32:30 *41:15 0.000343237
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 user_gpio_oeb *41:15 46.8745
2 *41:15 *41:33 43.7411
3 *41:33 *173:DIODE 26.4339
4 *41:15 *316:A0 9.3
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *42 0.0126066
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P user_gpio_out I
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *317:B I *D sky130_fd_sc_hd__nand2b_2
*I *174:DIODE I *D sky130_fd_sc_hd__diode_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 user_gpio_out 0.00168402
2 *317:B 0
3 *174:DIODE 7.81945e-05
4 *42:28 0.00161944
5 *42:10 0.00322526
6 *42:10 *416:A 0.000112897
7 *42:10 *102:16 0.000279169
8 *42:10 *103:11 4.88209e-05
9 *42:28 *311:A 0.00130399
10 *42:28 *316:A1 7.92497e-06
11 *42:28 *321:B1 0.000884464
12 *42:28 *329:A_N 6.27782e-05
13 *42:28 *367:RESET_B 0.00119634
14 *42:28 *369:SET_B 0.000155613
15 *42:28 *404:A 2.51196e-05
16 *42:28 *78:22 6.89682e-05
17 *42:28 *102:16 2.41211e-05
18 *42:28 *109:11 0.000693738
19 *176:DIODE *42:28 3.84567e-05
20 *182:DIODE *42:10 5.83017e-05
21 *189:DIODE *42:28 5.04829e-06
22 *212:DIODE *42:28 0.000198655
23 *338:B *42:10 0.000118002
24 *340:B *42:10 0.000118017
25 *13:45 *42:10 0.000186268
26 *18:5 *174:DIODE 0.000109427
27 *26:8 *42:28 1.10133e-05
28 *33:18 *42:10 0.000183821
29 *33:18 *42:28 2.44669e-05
30 *41:15 *42:10 8.4215e-05
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 user_gpio_out *42:10 26.4211
2 *42:10 *42:28 49.6766
3 *42:28 *174:DIODE 14.7464
4 *42:10 *317:B 9.3
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *47 0.00598856
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*CONN
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*P zero O
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *442:X O *D sky130_fd_sc_hd__buf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 zero 0.0021565
2 *442:X 0.0021565
3 mgmt_gpio_in zero 0.000470254
4 one zero 0.000997543
5 *211:DIODE zero 0.000207768
6 *15:8 zero 0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *442:X zero 27.1098
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *48 0.00233044
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *319:A_N I *D sky130_fd_sc_hd__and2b_2
*I *367:Q_N O *D sky130_fd_sc_hd__dfbbn_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *319:A_N 0.000368677
2 *367:Q_N 0.000368677
3 *319:A_N *369:SET_B 4.21731e-05
4 *319:A_N *400:A 6.36477e-05
5 *319:A_N *425:A 0.00062672
6 *319:A_N *69:8 1.36905e-05
7 pad_gpio_dm[0] *319:A_N 6.08467e-05
8 *212:DIODE *319:A_N 0.00078601
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *367:Q_N *319:A_N 39.1893
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *49 0.00243794
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *404:A I *D sky130_fd_sc_hd__einvp_8
*I *311:Y O *D sky130_fd_sc_hd__inv_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *404:A 0.000713593
2 *311:Y 0.000713593
3 *404:A *319:B 0.000169504
4 *404:A *320:A1 0.000107425
5 *404:A *321:A1 1.5714e-05
6 *404:A *321:A2 3.85446e-05
7 *404:A *367:RESET_B 0.00040582
8 *404:A *78:22 0.000143917
9 *214:DIODE *404:A 0.00010471
10 *42:28 *404:A 2.51196e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *311:Y *404:A 44.1179
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *50 0.000434747
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *360:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *322:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *360:RESET_B 0.000182536
2 *322:X 0.000182536
3 *360:RESET_B *322:A 0
4 *360:RESET_B *360:CLK_N 6.96754e-05
5 *322:B *360:RESET_B 0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *322:X *360:RESET_B 30.9036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *51 0.00576622
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *360:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *323:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *360:SET_B 0.000806108
2 *323:Y 0.000277508
3 *51:17 0.00108362
4 *360:SET_B *326:A 9.87116e-05
5 *360:SET_B *347:A_N 0.000190001
6 *360:SET_B *372:SET_B 5.77533e-06
7 *360:SET_B *385:D 0.00018014
8 *360:SET_B *427:A 0.00171725
9 *360:SET_B *145:28 4.99584e-05
10 *51:17 *388:A 8.58199e-05
11 *51:17 *388:TE_B 3.64303e-05
12 *51:17 *106:29 8.33134e-05
13 *51:17 *121:7 5.73753e-05
14 *51:17 *145:28 0.000200635
15 *205:DIODE *51:17 0.000160942
16 *1:45 *360:SET_B 0
17 *3:22 *360:SET_B 0.00073007
18 *32:43 *360:SET_B 2.57465e-06
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *323:Y *51:17 29.7464
2 *51:17 *360:SET_B 28.3036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *52 0.00466917
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *361:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *324:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *361:RESET_B 0.00193217
2 *324:X 0.00193217
3 *361:RESET_B *361:CLK_N 0.000175018
4 *361:RESET_B *386:D 6.26025e-05
5 *361:RESET_B *386:RESET_B 0.000307892
6 *361:RESET_B *116:48 6.27782e-05
7 *361:RESET_B *137:13 0.000143668
8 *34:16 *361:RESET_B 5.28741e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *324:X *361:RESET_B 42.4036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *53 0.00991253
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *361:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *325:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *361:SET_B 0.001219
2 *325:Y 0.000786085
3 *53:10 0.00200509
4 *361:SET_B *365:SET_B 0.00148979
5 *361:SET_B *366:SET_B 0.00122527
6 *361:SET_B *63:10 0.000521497
7 *361:SET_B *111:8 0.000111152
8 *53:10 *365:SET_B 0.000237114
9 *53:10 *63:10 0.000262294
10 *180:DIODE *53:10 0.000358585
11 *190:DIODE *53:10 9.72686e-05
12 *333:B *53:10 0.000317553
13 *6:28 *53:10 6.64392e-05
14 *6:36 *53:10 0.000167438
15 *12:10 *361:SET_B 0.00091077
16 *13:9 *361:SET_B 0.000137193
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *325:Y *53:10 31.8446
2 *53:10 *361:SET_B 42.5446
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *54 0.00406907
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *362:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *326:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *362:RESET_B 0
2 *326:X 0.00119314
3 *54:16 0.00119314
4 *54:16 *312:A 0
5 *54:16 *362:SET_B 0.000478595
6 *54:16 *382:CLK 2.57986e-05
7 *54:16 *382:D 0.000138356
8 *54:16 *382:RESET_B 2.57494e-05
9 *54:16 *384:D 2.77543e-05
10 *54:16 *407:A 0.000140383
11 *54:16 *67:10 3.11285e-05
12 *54:16 *110:17 3.06847e-05
13 *54:16 *121:36 1.07403e-05
14 *54:16 *121:51 0.000272378
15 pad_gpio_vtrip_sel *54:16 4.56572e-05
16 *2:21 *54:16 0.000455566
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *326:X *54:16 41.4042
2 *54:16 *362:RESET_B 9.3
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *55 0.00188766
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *362:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *327:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *362:SET_B 0.000378894
2 *327:Y 0.000378894
3 *362:SET_B *323:A_N 5.21049e-05
4 *362:SET_B *367:SET_B 1.68207e-05
5 *362:SET_B *399:A 0.000130079
6 *362:SET_B *67:10 2.78569e-05
7 *362:SET_B *110:17 6.93171e-05
8 *362:SET_B *120:32 0.000147046
9 *362:SET_B *121:36 0.000205476
10 *362:SET_B *121:51 2.57465e-06
11 *54:16 *362:SET_B 0.000478595
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *327:Y *362:SET_B 28.2196
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *56 0.000809475
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *363:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *328:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *363:RESET_B 0.000209277
2 *328:X 0.000209277
3 *363:RESET_B *315:A 0.000143175
4 *363:RESET_B *100:24 0.000143175
5 *363:RESET_B *110:17 0.000104572
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *328:X *363:RESET_B 32.1357
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *57 0.00146477
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *363:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *329:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *363:SET_B 0.000244875
2 *329:Y 0.000244875
3 *363:SET_B *369:SET_B 0.000485188
4 *363:SET_B *109:11 0.000489834
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *329:Y *363:SET_B 25.4071
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *58 0.0026405
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *364:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *330:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *364:RESET_B 0.000622377
2 *330:X 0.000622377
3 *364:RESET_B *373:RESET_B 0.000105882
4 *364:RESET_B *116:39 7.19065e-05
5 *364:RESET_B *141:16 0.000601934
6 *364:RESET_B *145:28 3.16356e-05
7 *2:21 *364:RESET_B 0.00036264
8 *33:18 *364:RESET_B 0.000221746
9 *34:16 *364:RESET_B 0
10 *34:21 *364:RESET_B 0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *330:X *364:RESET_B 42.1893
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *59 0.00295744
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *364:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *331:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *364:SET_B 0.00122177
2 *331:Y 0.00122177
3 *364:SET_B *376:CLK 7.12487e-06
4 *364:SET_B *376:D 7.60548e-05
5 *364:SET_B *376:RESET_B 3.99387e-05
6 *364:SET_B *414:A 4.47179e-05
7 *364:SET_B *111:8 8.69298e-05
8 *364:SET_B *142:10 0.00016553
9 *364:SET_B *143:10 6.06556e-06
10 *11:17 *364:SET_B 6.07304e-07
11 *12:10 *364:SET_B 8.69298e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *331:Y *364:SET_B 32.1036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *60 0.00151838
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *365:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *332:X O *D sky130_fd_sc_hd__or2_0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *365:RESET_B 0.000335777
2 *332:X 0.000335777
3 *365:RESET_B *376:RESET_B 1.03403e-05
4 *365:RESET_B *410:A 0.00013697
5 *365:RESET_B *114:15 1.66398e-05
6 *365:RESET_B *114:27 0.000347266
7 *365:RESET_B *115:14 5.71992e-05
8 *365:RESET_B *157:28 2.16355e-05
9 *2:21 *365:RESET_B 0.0001045
10 *11:17 *365:RESET_B 5.9951e-05
11 *12:18 *365:RESET_B 9.23267e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *332:X *365:RESET_B 35.475
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *61 0.00709783
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *365:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *333:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *365:SET_B 0.00104247
2 *333:Y 0.00121494
3 *61:11 0.0022574
4 *365:SET_B *370:D 0.000106132
5 *365:SET_B *371:D 0.000396928
6 *365:SET_B *111:8 0.000158272
7 *365:SET_B *147:8 8.96342e-05
8 *188:DIODE *61:11 8.85947e-05
9 *192:DIODE *61:11 7.94337e-06
10 *333:B *61:11 8.61152e-06
11 *361:SET_B *365:SET_B 0.00148979
12 *53:10 *365:SET_B 0.000237114
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *333:Y *61:11 36.175
2 *61:11 *365:SET_B 31.6429
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *62 0.00247207
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *366:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *334:X O *D sky130_fd_sc_hd__or2_0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *366:RESET_B 0.000475431
2 *334:X 0.000475431
3 *366:RESET_B *126:10 0.000171988
4 *366:RESET_B *141:16 0.000180295
5 *366:RESET_B *164:16 0.000127809
6 *389:A *366:RESET_B 0.000482556
7 *13:9 *366:RESET_B 0.000480081
8 *34:21 *366:RESET_B 7.84839e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *334:X *366:RESET_B 40.8143
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *63 0.0073367
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *366:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *335:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *366:SET_B 0.000533742
2 *335:Y 0.000991128
3 *63:10 0.00152487
4 *366:SET_B *370:SET_B 1.82249e-05
5 *366:SET_B *379:RESET_B 0.000335932
6 *366:SET_B *418:A 2.28034e-05
7 *366:SET_B *126:10 6.47907e-05
8 *63:10 *185:DIODE 1.43832e-05
9 *63:10 *370:SET_B 0.000950894
10 *63:10 *116:91 2.41827e-05
11 *63:10 *116:97 2.44599e-05
12 *204:DIODE *63:10 0.000259547
13 *361:SET_B *366:SET_B 0.00122527
14 *361:SET_B *63:10 0.000521497
15 *11:17 *366:SET_B 0.000267612
16 *13:9 *366:SET_B 0.000205669
17 *34:21 *63:10 8.94038e-05
18 *53:10 *63:10 0.000262294
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *335:Y *63:10 38.5768
2 *63:10 *366:SET_B 21.1696
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *64 0.00380933
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *367:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *336:X O *D sky130_fd_sc_hd__or2_0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *367:RESET_B 0.0007419
2 *336:X 0.0007419
3 *367:RESET_B *311:A 8.34211e-06
4 *367:RESET_B *321:A2 3.85446e-05
5 *367:RESET_B *425:A 0.000233783
6 *367:RESET_B *439:A 0.000110949
7 pad_gpio_ana_pol *367:RESET_B 1.88563e-05
8 *176:DIODE *367:RESET_B 0.000142069
9 *214:DIODE *367:RESET_B 0.000108053
10 *404:A *367:RESET_B 0.00040582
11 *36:8 *367:RESET_B 6.27718e-05
12 *42:28 *367:RESET_B 0.00119634
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *336:X *367:RESET_B 48.2607
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *65 0.00288401
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *367:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *337:Y O *D sky130_fd_sc_hd__nand2b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *367:SET_B 0.000701823
2 *337:Y 0.000701823
3 *367:SET_B *323:A_N 0.00054154
4 *367:SET_B *383:RESET_B 4.28856e-07
5 *367:SET_B *384:D 7.26748e-05
6 *367:SET_B *120:32 3.02761e-06
7 *367:SET_B *153:10 0.000400271
8 *362:SET_B *367:SET_B 1.68207e-05
9 *13:66 *367:SET_B 0.000445596
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *337:Y *367:SET_B 31.2821
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *66 0.0020485
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *368:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *338:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *368:RESET_B 0.00055845
2 *338:X 0.00055845
3 *368:RESET_B *338:A 6.27782e-05
4 *368:RESET_B *340:A 6.08467e-05
5 *368:RESET_B *369:RESET_B 0.000341729
6 *368:RESET_B *99:14 0.000149923
7 *368:RESET_B *100:22 6.1578e-06
8 *368:RESET_B *103:11 0.000310161
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *338:X *368:RESET_B 39.5821
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *67 0.00621005
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *368:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *339:Y O *D sky130_fd_sc_hd__nand2b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *368:SET_B 8.91202e-05
2 *339:Y 0.00105265
3 *67:10 0.00114177
4 *368:SET_B *99:14 1.83545e-05
5 *67:10 *369:SET_B 0.00209889
6 *67:10 *399:A 3.08084e-05
7 *67:10 *400:A 1.3262e-05
8 *67:10 *407:A 0.00031441
9 *67:10 *430:A 0.000137252
10 *67:10 *121:8 3.42037e-06
11 *67:10 *121:51 0.000284801
12 *67:10 *162:8 0.000198119
13 *327:B *67:10 2.08648e-05
14 *339:B *67:10 6.36477e-05
15 *362:SET_B *67:10 2.78569e-05
16 *13:66 *67:10 0.000673362
17 *35:13 *67:10 1.03403e-05
18 *54:16 *67:10 3.11285e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *339:Y *67:10 48.7107
2 *67:10 *368:SET_B 1.29464
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *68 0.0012172
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *369:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *340:X O *D sky130_fd_sc_hd__or2_0
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *369:RESET_B 0.000335361
2 *340:X 0.000335361
3 *369:RESET_B *338:A 0
4 *369:RESET_B *416:A 2.41274e-06
5 *369:RESET_B *100:22 0.000164114
6 *369:RESET_B *103:11 3.82228e-05
7 *368:RESET_B *369:RESET_B 0.000341729
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *340:X *369:RESET_B 34.8679
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *69 0.00724817
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *369:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *341:Y O *D sky130_fd_sc_hd__nand2b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *369:SET_B 0.00144248
2 *341:Y 9.45623e-05
3 *69:8 0.00153704
4 *369:SET_B *369:D 1.13359e-05
5 *369:SET_B *400:A 9.87169e-05
6 *369:SET_B *425:A 0.000646231
7 *369:SET_B *78:22 6.53188e-05
8 *369:SET_B *100:22 5.12261e-05
9 *369:SET_B *109:11 0.000350093
10 *369:SET_B *162:8 8.35027e-05
11 *69:8 *400:A 7.14062e-05
12 *212:DIODE *369:SET_B 7.03786e-07
13 *319:A_N *369:SET_B 4.21731e-05
14 *319:A_N *69:8 1.36905e-05
15 *363:SET_B *369:SET_B 0.000485188
16 *42:28 *369:SET_B 0.000155613
17 *67:10 *369:SET_B 0.00209889
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *341:Y *69:8 15.3982
2 *69:8 *369:SET_B 42.5446
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *70 0.0012127
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *370:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *342:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *370:RESET_B 0.000290256
2 *342:X 0.000290256
3 *370:RESET_B *354:A 1.65872e-05
4 *370:RESET_B *367:CLK_N 2.16355e-05
5 *370:RESET_B *97:5 2.16355e-05
6 *370:RESET_B *98:17 0.000200794
7 *370:RESET_B *119:29 0.000145794
8 *370:RESET_B *132:6 0.000134976
9 *14:12 *370:RESET_B 2.77625e-06
10 *35:13 *370:RESET_B 8.79845e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *342:X *370:RESET_B 33.9036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *71 0.00559707
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *370:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *343:Y O *D sky130_fd_sc_hd__nand2b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *370:SET_B 0.00145368
2 *343:Y 0.00145368
3 *370:SET_B *343:A_N 0.000205681
4 *370:SET_B *381:CLK 2.16355e-05
5 *370:SET_B *381:D 0.000117562
6 *370:SET_B *418:A 0.00013832
7 *370:SET_B *96:25 1.54577e-05
8 *370:SET_B *157:7 6.08467e-05
9 *343:B *370:SET_B 1.65872e-05
10 *366:SET_B *370:SET_B 1.82249e-05
11 *9:14 *370:SET_B 0.000587064
12 *14:8 *370:SET_B 0.000328421
13 *34:21 *370:SET_B 0.000229019
14 *63:10 *370:SET_B 0.000950894
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *343:Y *370:SET_B 45.7464
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *72 0.00230351
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *371:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *344:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *371:RESET_B 0.000497794
2 *344:X 0.000497794
3 *371:RESET_B *344:A 6.08467e-05
4 *371:RESET_B *349:A 6.96979e-05
5 *371:RESET_B *362:CLK_N 1.9898e-05
6 *371:RESET_B *388:TE_B 0.000194724
7 *371:RESET_B *428:A 7.04483e-05
8 *371:RESET_B *158:70 0.000186579
9 *3:27 *371:RESET_B 0.000404483
10 *4:21 *371:RESET_B 1.42851e-05
11 *11:33 *371:RESET_B 0.000196745
12 *11:58 *371:RESET_B 3.54024e-05
13 *39:16 *371:RESET_B 5.481e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *344:X *371:RESET_B 39.2429
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *73 0.00115425
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *371:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *345:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *371:SET_B 0.000522313
2 *345:Y 0.000522313
3 *371:SET_B *371:CLK_N 7.13972e-05
4 *371:SET_B *371:D 3.82228e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *345:Y *371:SET_B 15.2732
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *74 0.00103992
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *372:RESET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *346:X O *D sky130_fd_sc_hd__or2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *372:RESET_B 0.000194957
2 *346:X 0.000194957
3 *372:RESET_B *347:A_N 0.00015607
4 *372:RESET_B *367:D 0.000143175
5 *372:RESET_B *145:28 0.000143175
6 *32:43 *372:RESET_B 0.000207591
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *346:X *372:RESET_B 32.5464
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *75 0.00137432
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *372:SET_B I *D sky130_fd_sc_hd__dfbbn_2
*I *347:Y O *D sky130_fd_sc_hd__nand2b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *372:SET_B 0.000262315
2 *347:Y 0.000262315
3 *372:SET_B *347:A_N 8.66674e-05
4 *372:SET_B *367:CLK_N 0.000141811
5 *372:SET_B *145:28 0.000476565
6 *360:SET_B *372:SET_B 5.77533e-06
7 *3:22 *372:SET_B 8.70662e-06
8 *32:43 *372:SET_B 0.000130164
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *347:Y *372:SET_B 25.6839
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *76 0.00295445
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *316:A1 I *D sky130_fd_sc_hd__mux2_4
*I *315:X O *D sky130_fd_sc_hd__and2_0
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *316:A1 0.000665949
2 *315:X 0.000665949
3 *316:A1 *321:A1 0.000403346
4 *316:A1 *321:A2 0.000433352
5 *316:A1 *78:22 1.79916e-05
6 *316:A1 *102:16 3.93627e-05
7 *316:A1 *103:11 0.000431721
8 *176:DIODE *316:A1 3.49685e-05
9 *13:66 *316:A1 0.000208834
10 *26:8 *316:A1 4.50545e-05
11 *42:28 *316:A1 7.92497e-06
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *315:X *316:A1 48.577
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *77 0.00228786
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *321:B1 I *D sky130_fd_sc_hd__o21ai_4
*I *317:Y O *D sky130_fd_sc_hd__nand2b_2
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *321:B1 0.000502006
2 *317:Y 0.000502006
3 *321:B1 *102:16 0.000339303
4 *33:18 *321:B1 6.00813e-05
5 *42:28 *321:B1 0.000884464
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *317:Y *321:B1 40.2071
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *78 0.0045143
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *320:A2 I *D sky130_fd_sc_hd__o21ai_2
*I *319:B I *D sky130_fd_sc_hd__and2b_2
*I *318:X O *D sky130_fd_sc_hd__and3b_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *320:A2 0
2 *319:B 0.000251204
3 *318:X 0.000935848
4 *78:22 0.00118705
5 *319:B *320:A1 0.000400152
6 *319:B *321:A1 1.5714e-05
7 *319:B *400:A 6.55312e-05
8 *319:B *426:A 1.22289e-05
9 *78:22 *318:C 0
10 *78:22 *320:B1 0.000651386
11 *78:22 *425:A 0
12 *78:22 *426:A 1.07403e-05
13 pad_gpio_out *78:22 0.000124363
14 *176:DIODE *78:22 4.87242e-05
15 *316:A1 *78:22 1.79916e-05
16 *369:SET_B *78:22 6.53188e-05
17 *404:A *319:B 0.000169504
18 *404:A *78:22 0.000143917
19 *26:8 *78:22 0.000345659
20 *42:28 *78:22 6.89682e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *318:X *78:22 42.9578
2 *78:22 *319:B 20.7464
3 *78:22 *320:A2 13.8
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *79 0.00484776
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *321:A1 I *D sky130_fd_sc_hd__o21ai_4
*I *319:X O *D sky130_fd_sc_hd__and2b_2
*CAP
1 *321:A1 0.00203308
2 *319:X 0.00203308
3 *321:A1 *321:A2 0.000152185
4 *321:A1 *102:16 8.35235e-06
5 *321:A1 *103:11 1.09898e-05
6 pad_gpio_dm[0] *321:A1 6.27782e-05
7 *316:A1 *321:A1 0.000403346
8 *319:B *321:A1 1.5714e-05
9 *404:A *321:A1 1.5714e-05
10 *26:8 *321:A1 5.76799e-05
11 *32:30 *321:A1 5.48401e-05
*RES
1 *319:X *321:A1 47.7426
*END
*D_NET *80 0.00342825
*CONN
*I *321:A2 I *D sky130_fd_sc_hd__o21ai_4
*I *320:Y O *D sky130_fd_sc_hd__o21ai_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *321:A2 0.00135397
2 *320:Y 0.00135397
3 *321:A2 *102:16 2.02035e-05
4 pad_gpio_dm[1] *321:A2 2.62319e-05
5 *316:A1 *321:A2 0.000433352
6 *321:A1 *321:A2 0.000152185
7 *367:RESET_B *321:A2 3.85446e-05
8 *404:A *321:A2 3.85446e-05
9 *26:8 *321:A2 1.12517e-05
*RES
1 *320:Y *321:A2 44.6602
*END
*D_NET *81 0.00884911
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *388:TE_B I *D sky130_fd_sc_hd__ebufn_8
*I *314:Y O *D sky130_fd_sc_hd__nand2b_2
*CAP
1 *388:TE_B 0.000936716
2 *314:Y 0.000929297
3 *81:10 0.00186601
4 *388:TE_B *323:A_N 0.000159908
5 *388:TE_B *388:A 4.7457e-05
6 *388:TE_B *417:A 4.2372e-05
7 *388:TE_B *428:A 0.000156506
8 *388:TE_B *98:17 3.54295e-05
9 *81:10 *315:A 0.00120443
10 *81:10 *318:C 0.000194952
11 *81:10 *426:A 2.51664e-05
12 *81:10 *101:8 0.000134976
13 *81:10 *118:19 0
14 *81:10 *118:28 0
15 *81:10 *118:41 7.78924e-05
16 *81:10 *120:52 0.000271402
17 *205:DIODE *388:TE_B 3.73474e-05
18 *206:DIODE *388:TE_B 0.000109884
19 *347:B *388:TE_B 4.76161e-06
20 *371:RESET_B *388:TE_B 0.000194724
21 *3:27 *388:TE_B 6.84074e-06
22 *11:58 *388:TE_B 0.000694781
23 *39:16 *388:TE_B 0.00165159
24 *40:7 *388:TE_B 3.02384e-05
25 *51:17 *388:TE_B 3.64303e-05
*RES
1 *314:Y *81:10 41.1393
2 *81:10 *388:TE_B 42.8536
*END
*D_NET *94 0.00412701
*CONN
*I *393:A I *D sky130_fd_sc_hd__clkbuf_16
*I *391:A I *D sky130_fd_sc_hd__clkbuf_16
*I *389:X O *D sky130_fd_sc_hd__clkbuf_16
*CAP
1 *393:A 2.43095e-05
2 *391:A 0.000270678
3 *389:X 0.000893912
4 *94:8 0.0011889
5 *391:A *365:CLK_N 0.000208621
6 *94:8 *414:A 5.1623e-05
7 *213:DIODE *391:A 9.28161e-05
8 *343:B *393:A 6.27782e-05
9 *5:16 *94:8 6.27782e-05
10 *6:19 *391:A 0.000122114
11 *6:19 *94:8 0.000673015
12 *7:11 *94:8 0.000189637
13 *7:19 *391:A 8.06761e-05
14 *7:19 *94:8 0.000205148
*RES
1 *389:X *94:8 35.4071
2 *94:8 *391:A 20.2464
3 *94:8 *393:A 14.3357
*END
*D_NET *95 0.00502941
*CONN
*I *394:A I *D sky130_fd_sc_hd__clkbuf_16
*I *392:A I *D sky130_fd_sc_hd__clkbuf_16
*I *390:X O *D sky130_fd_sc_hd__clkbuf_16
*CAP
1 *394:A 0
2 *392:A 0.000337121
3 *390:X 0.000867287
4 *95:8 0.00120441
5 *392:A *440:A 0.000257331
6 *392:A *98:17 2.58757e-05
7 *392:A *114:83 0.000334612
8 *95:8 *373:CLK 0.000178277
9 *95:8 *408:A 0.000291452
10 *95:8 *440:A 0.000141811
11 *95:8 *157:21 0.000176793
12 *173:DIODE *95:8 0.000242322
13 *342:B *392:A 8.36586e-06
14 *8:19 *392:A 8.272e-05
15 *8:19 *95:8 8.02727e-05
16 *9:35 *392:A 0.000512904
17 *41:33 *95:8 0.000287858
*RES
1 *390:X *95:8 28.5321
2 *95:8 *392:A 24.175
3 *95:8 *394:A 13.8
*END
*D_NET *96 0.0132928
*CONN
*I *380:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *381:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *375:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *374:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *376:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *377:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *379:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *378:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *313:A I *D sky130_fd_sc_hd__inv_2
*I *391:X O *D sky130_fd_sc_hd__clkbuf_16
*CAP
1 *380:CLK 1.69747e-05
2 *381:CLK 2.90725e-05
3 *375:CLK 0.000879793
4 *374:CLK 0
5 *376:CLK 0.000171348
6 *377:CLK 0.00024576
7 *379:CLK 0
8 *378:CLK 0.000353467
9 *313:A 0.000607384
10 *391:X 9.08552e-05
11 *96:68 0.00115976
12 *96:56 0.00054901
13 *96:41 0.000388737
14 *96:34 0.000122488
15 *96:25 0.000716422
16 *96:19 0.000470101
17 *96:7 0.000762666
18 *96:5 0.00010783
19 *313:A *114:55 8.92089e-05
20 *313:A *114:66 0.000151258
21 *313:A *116:91 6.64392e-05
22 *313:A *137:13 0.000240136
23 *375:CLK *366:D 0.000442556
24 *375:CLK *373:CLK 0.000143161
25 *375:CLK *375:D 0.000167934
26 *375:CLK *129:15 6.12919e-06
27 *376:CLK *376:D 5.04829e-06
28 *377:CLK *433:A 4.46267e-05
29 *378:CLK *378:D 0.000325455
30 *380:CLK *403:A 1.65872e-05
31 *96:5 *403:A 2.16355e-05
32 *96:5 *114:83 6.08467e-05
33 *96:25 *386:RESET_B 0.000194842
34 *96:34 *386:RESET_B 0.000153477
35 *96:41 *386:RESET_B 0.00014603
36 *96:56 *386:RESET_B 0.000190134
37 *96:68 *373:CLK 0.000221977
38 *96:68 *376:D 7.78924e-05
39 *204:DIODE *313:A 6.3657e-05
40 *209:DIODE *96:25 0.000198319
41 *209:DIODE *96:34 0.000145111
42 *209:DIODE *96:41 4.94462e-05
43 *213:DIODE *96:5 0.000111802
44 *364:SET_B *376:CLK 7.12487e-06
45 *370:SET_B *381:CLK 2.16355e-05
46 *370:SET_B *96:25 1.54577e-05
47 *5:29 *313:A 0.00121064
48 *5:29 *96:19 0.000346414
49 *5:33 *313:A 9.89388e-06
50 *8:11 *375:CLK 5.49769e-05
51 *8:11 *96:68 7.5617e-05
52 *8:19 *96:68 1.48262e-05
53 *9:14 *96:25 0.000342667
54 *10:20 *313:A 0.000346927
55 *10:20 *96:19 0.000351188
56 *32:43 *380:CLK 6.08467e-05
57 *32:43 *96:5 0.000139947
58 *38:8 *96:41 0.000101177
59 *38:8 *96:56 0.000188094
*RES
1 *391:X *96:5 11.4786
2 *96:5 *96:7 4.5
3 *96:7 *313:A 31.4607
4 *96:7 *96:19 9.48214
5 *96:19 *96:25 11.3036
6 *96:25 *378:CLK 21.3179
7 *96:25 *96:34 2.25
8 *96:34 *379:CLK 13.8
9 *96:34 *96:41 1.94643
10 *96:41 *377:CLK 17.2464
11 *96:41 *96:56 7.05357
12 *96:56 *376:CLK 11.3893
13 *96:56 *96:68 9.42857
14 *96:68 *374:CLK 13.8
15 *96:68 *375:CLK 25.6393
16 *96:19 *381:CLK 9.83571
17 *96:5 *380:CLK 9.83571
*END
*D_NET *97 0.0104837
*CONN
*I *354:A I *D sky130_fd_sc_hd__inv_2
*I *349:A I *D sky130_fd_sc_hd__inv_2
*I *359:A I *D sky130_fd_sc_hd__inv_2
*I *358:A I *D sky130_fd_sc_hd__inv_2
*I *352:A I *D sky130_fd_sc_hd__inv_2
*I *357:A I *D sky130_fd_sc_hd__inv_2
*I *392:X O *D sky130_fd_sc_hd__clkbuf_16
*CAP
1 *354:A 4.33919e-05
2 *349:A 0.000515392
3 *359:A 3.21456e-05
4 *358:A 0
5 *352:A 0.000112205
6 *357:A 0.000189161
7 *392:X 7.15262e-05
8 *97:36 0.000762968
9 *97:24 0.00121815
10 *97:19 0.00135059
11 *97:7 0.000489118
12 *97:5 0.000114918
13 *349:A *362:CLK_N 0.00028688
14 *349:A *428:A 6.49279e-05
15 *349:A *146:11 3.82228e-05
16 *349:A *157:31 0.000224425
17 *349:A *158:46 9.80242e-07
18 *349:A *158:70 5.429e-05
19 *352:A *116:53 4.11616e-05
20 *352:A *158:10 1.37566e-05
21 *357:A *441:A 0.000161817
22 *357:A *158:51 0.000387111
23 *97:5 *98:17 7.5301e-06
24 *97:5 *114:27 6.36477e-05
25 *97:5 *114:33 3.89073e-05
26 *97:19 *381:D 5.71849e-05
27 *97:19 *114:27 4.86863e-05
28 *97:19 *115:20 0.000210452
29 *97:19 *132:6 3.01773e-05
30 *97:19 *158:51 0.000650015
31 *97:24 *372:CLK_N 0.000209802
32 *97:24 *158:46 1.25805e-05
33 *97:36 *408:A 0.000164656
34 *97:36 *114:83 0.00026225
35 *97:36 *149:7 6.08467e-05
36 *97:36 *158:10 0.000104653
37 *97:36 *158:46 0.000823384
38 *209:DIODE *97:36 0.000255038
39 *342:B *97:5 6.64392e-05
40 *344:B *349:A 1.99596e-06
41 *370:RESET_B *354:A 1.65872e-05
42 *370:RESET_B *97:5 2.16355e-05
43 *371:RESET_B *349:A 6.96979e-05
44 *11:33 *349:A 6.65668e-05
45 *11:41 *97:19 0.000205476
46 *14:12 *354:A 2.16355e-05
47 *14:12 *97:5 0.000127795
48 *35:10 *357:A 6.84074e-06
49 *39:10 *357:A 0.000474181
50 *39:10 *97:19 0.000231952
*RES
1 *392:X *97:5 11.8893
2 *97:5 *97:7 4.5
3 *97:7 *357:A 20.4429
4 *97:7 *97:19 14.9464
5 *97:19 *97:24 6.42857
6 *97:24 *97:36 15.1071
7 *97:36 *352:A 20.55
8 *97:36 *358:A 9.3
9 *97:24 *359:A 10.0321
10 *97:19 *349:A 27.6929
11 *97:5 *354:A 10.2643
*END
*D_NET *98 0.00676075
*CONN
*I *404:TE I *D sky130_fd_sc_hd__einvp_8
*I *405:gpio_logic1 O *D gpio_logic_high
*CAP
1 *404:TE 0
2 *405:gpio_logic1 0.00247482
3 *98:17 0.00247482
4 *98:17 *323:A_N 6.27782e-05
5 *98:17 *367:CLK_N 0.000121018
6 *98:17 *431:A 5.7657e-05
7 *98:17 *114:27 2.28961e-05
8 *98:17 *114:33 0.000737026
9 *98:17 *153:10 0.000228215
10 pad_gpio_ib_mode_sel *98:17 6.08467e-05
11 *205:DIODE *98:17 5.04829e-06
12 *342:B *98:17 8.29362e-05
13 *370:RESET_B *98:17 0.000200794
14 *388:TE_B *98:17 3.54295e-05
15 *392:A *98:17 2.58757e-05
16 *7:19 *98:17 5.37732e-05
17 *14:12 *98:17 3.38969e-05
18 *24:9 *98:17 7.54013e-05
19 *97:5 *98:17 7.5301e-06
*RES
1 *405:gpio_logic1 *98:17 47.9797
2 *98:17 *404:TE 9.3
*END
*D_NET *99 0.00795564
*CONN
*I *314:B I *D sky130_fd_sc_hd__nand2b_2
*I *315:A I *D sky130_fd_sc_hd__and2_0
*I *366:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *314:B 0
2 *315:A 0.000661455
3 *366:Q 0.00163642
4 *99:14 0.00229787
5 *315:A *315:B 2.58757e-05
6 *315:A *320:B1 0.000201584
7 *315:A *426:A 0.00017521
8 *315:A *100:22 0.000163045
9 *315:A *100:24 0.000294838
10 *99:14 *340:A 0.000109427
11 *99:14 *368:CLK_N 3.96696e-05
12 *99:14 *368:D 1.19705e-05
13 *99:14 *373:RESET_B 2.47178e-05
14 *99:14 *100:22 0.000136159
15 *99:14 *102:16 1.8254e-05
16 *99:14 *145:28 0.00058242
17 *176:DIODE *315:A 6.08467e-05
18 *363:RESET_B *315:A 0.000143175
19 *368:RESET_B *99:14 0.000149923
20 *368:SET_B *99:14 1.83545e-05
21 *81:10 *315:A 0.00120443
*RES
1 *366:Q *99:14 34.4607
2 *99:14 *315:A 33.9429
3 *99:14 *314:B 13.8
*END
*D_NET *100 0.00869123
*CONN
*I *317:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *316:S I *D sky130_fd_sc_hd__mux2_4
*I *320:B1 I *D sky130_fd_sc_hd__o21ai_2
*I *360:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *317:A_N 3.37551e-05
2 *316:S 0.000139572
3 *320:B1 0.000620273
4 *360:Q 0.000794389
5 *100:24 0.000999819
6 *100:22 0.00106812
7 *320:B1 *339:A_N 7.45746e-05
8 *320:B1 *426:A 0.000704387
9 *320:B1 *103:11 0.00048062
10 *100:22 *338:A 0
11 *100:22 *360:CLK_N 0.000171651
12 *100:22 *369:D 0.000161252
13 *100:22 *398:A 9.50413e-05
14 *100:22 *399:A 4.45999e-05
15 *100:22 *103:11 0.000327773
16 *100:22 *109:11 4.80509e-05
17 *100:22 *116:15 0.000216304
18 *100:24 *103:11 0.000580899
19 *182:DIODE *100:22 2.61955e-05
20 *189:DIODE *317:A_N 2.16355e-05
21 *315:A *320:B1 0.000201584
22 *315:A *100:22 0.000163045
23 *315:A *100:24 0.000294838
24 *363:RESET_B *100:24 0.000143175
25 *368:RESET_B *100:22 6.1578e-06
26 *369:RESET_B *100:22 0.000164114
27 *369:SET_B *100:22 5.12261e-05
28 *32:30 *320:B1 2.57465e-06
29 *35:13 *320:B1 0.000196658
30 *41:15 *316:S 1.65872e-05
31 *41:33 *316:S 5.481e-05
32 *78:22 *320:B1 0.000651386
33 *99:14 *100:22 0.000136159
*RES
1 *360:Q *100:22 40.9786
2 *100:22 *100:24 8.01786
3 *100:24 *320:B1 32.7464
4 *100:24 *316:S 15.9964
5 *100:22 *317:A_N 14.3357
*END
*D_NET *101 0.00577044
*CONN
*I *318:C I *D sky130_fd_sc_hd__and3b_2
*I *315:B I *D sky130_fd_sc_hd__and2_0
*I *419:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *318:C 0.000235006
2 *315:B 0.000117103
3 *419:X 0.00109713
4 *101:8 0.00144924
5 *315:B *120:52 0.000107496
6 *318:C *426:A 4.66492e-05
7 *318:C *103:11 6.27718e-05
8 *318:C *120:52 0.000203317
9 *101:8 *120:52 0.000467997
10 pad_gpio_ana_pol *101:8 0.000637172
11 pad_gpio_out *318:C 0.000391301
12 *176:DIODE *315:B 3.38594e-05
13 *315:A *315:B 2.58757e-05
14 *2:38 *101:8 0.000485585
15 *32:30 *318:C 8.00035e-05
16 *78:22 *318:C 0
17 *81:10 *318:C 0.000194952
18 *81:10 *101:8 0.000134976
*RES
1 *419:X *101:8 35.4786
2 *101:8 *315:B 15.9786
3 *101:8 *318:C 20.6616
*END
*D_NET *102 0.00720741
*CONN
*I *318:B I *D sky130_fd_sc_hd__and3b_2
*I *425:A I *D sky130_fd_sc_hd__buf_16
*I *368:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *318:B 6.37874e-05
2 *425:A 0.000847913
3 *368:Q 0.00083247
4 *102:16 0.00174417
5 *425:A *311:A 8.91694e-05
6 *425:A *106:29 3.61024e-05
7 *425:A *123:8 6.93171e-05
8 pad_gpio_out *318:B 5.11592e-05
9 *176:DIODE *425:A 3.02163e-05
10 *189:DIODE *102:16 2.02035e-05
11 *212:DIODE *425:A 1.65736e-05
12 *212:DIODE *102:16 3.80838e-05
13 *316:A1 *102:16 3.93627e-05
14 *319:A_N *425:A 0.00062672
15 *321:A1 *102:16 8.35235e-06
16 *321:A2 *102:16 2.02035e-05
17 *321:B1 *102:16 0.000339303
18 *367:RESET_B *425:A 0.000233783
19 *369:SET_B *425:A 0.000646231
20 *2:21 *102:16 0.000583342
21 *13:45 *102:16 4.61048e-05
22 *13:66 *102:16 8.72115e-06
23 *26:8 *102:16 1.11698e-05
24 *32:30 *102:16 9.40549e-05
25 *33:18 *102:16 0.000389355
26 *42:10 *102:16 0.000279169
27 *42:28 *102:16 2.41211e-05
28 *78:22 *425:A 0
29 *99:14 *102:16 1.8254e-05
*RES
1 *368:Q *102:16 34.9429
2 *102:16 *425:A 41.0143
3 *102:16 *318:B 15.0545
*END
*D_NET *103 0.00865194
*CONN
*I *426:A I *D sky130_fd_sc_hd__buf_16
*I *318:A_N I *D sky130_fd_sc_hd__and3b_2
*I *369:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *426:A 0.000496642
2 *318:A_N 0
3 *369:Q 0.000799691
4 *103:11 0.00129633
5 *426:A *320:A1 0.000569788
6 *426:A *120:52 0.00107407
7 *181:DIODE *103:11 0.000556508
8 *182:DIODE *103:11 0.000418408
9 *315:A *426:A 0.00017521
10 *316:A1 *103:11 0.000431721
11 *318:C *426:A 4.66492e-05
12 *318:C *103:11 6.27718e-05
13 *319:B *426:A 1.22289e-05
14 *320:B1 *426:A 0.000704387
15 *320:B1 *103:11 0.00048062
16 *321:A1 *103:11 1.09898e-05
17 *368:RESET_B *103:11 0.000310161
18 *369:RESET_B *103:11 3.82228e-05
19 *13:66 *103:11 2.51664e-05
20 *32:30 *426:A 6.08467e-05
21 *32:30 *103:11 8.81178e-05
22 *42:10 *103:11 4.88209e-05
23 *78:22 *426:A 1.07403e-05
24 *81:10 *426:A 2.51664e-05
25 *100:22 *103:11 0.000327773
26 *100:24 *103:11 0.000580899
*RES
1 *369:Q *103:11 43.3179
2 *103:11 *318:A_N 9.3
3 *103:11 *426:A 36.5679
*END
*D_NET *104 0.00723317
*CONN
*I *427:A I *D sky130_fd_sc_hd__buf_16
*I *361:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *427:A 0.00118149
2 *361:Q 0.000105589
3 *104:7 0.00128708
4 *427:A *347:A_N 8.29571e-05
5 *427:A *367:CLK_N 3.67457e-05
6 *427:A *403:A 0.000143295
7 *427:A *412:A 0.000134662
8 *427:A *119:29 6.46815e-05
9 *427:A *164:16 0.000253078
10 *104:7 *369:CLK_N 0.000106653
11 *104:7 *386:D 0.000442865
12 *104:7 *140:8 0.000161243
13 pad_gpio_dm[1] *427:A 8.06639e-05
14 *322:B *427:A 7.02839e-06
15 *360:SET_B *427:A 0.00171725
16 *4:9 *427:A 7.43121e-05
17 *4:21 *427:A 0.00132771
18 *35:13 *427:A 2.58616e-05
*RES
1 *361:Q *104:7 17.5857
2 *104:7 *427:A 47.8536
*END
*D_NET *105 0.00259793
*CONN
*I *428:A I *D sky130_fd_sc_hd__buf_16
*I *365:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *428:A 0.0006265
2 *365:Q 0.0006265
3 *428:A *417:A 0.000147742
4 *428:A *132:6 0.000122893
5 *428:A *146:11 0.000126618
6 *428:A *157:28 1.8254e-05
7 *344:B *428:A 0.000114495
8 *349:A *428:A 6.49279e-05
9 *371:RESET_B *428:A 7.04483e-05
10 *388:TE_B *428:A 0.000156506
11 *3:27 *428:A 6.96741e-05
12 *11:33 *428:A 0.000299984
13 *11:58 *428:A 0.000153389
*RES
1 *365:Q *428:A 42.5107
*END
*D_NET *106 0.00850533
*CONN
*I *314:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *429:A I *D sky130_fd_sc_hd__buf_16
*I *364:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *314:A_N 0.000866692
2 *429:A 0
3 *364:Q 0.000526384
4 *106:29 0.00174274
5 *106:13 0.00313581
6 *314:A_N *326:A 7.31578e-05
7 *314:A_N *329:A_N 2.16355e-05
8 *314:A_N *118:41 0.000222225
9 *106:13 *326:A 9.08935e-05
10 *106:13 *385:CLK 1.88422e-05
11 *106:13 *396:A 0.000187087
12 *106:29 *312:A 0.000289166
13 *106:29 *362:D 0.000115333
14 *106:29 *367:D 0.000430405
15 *106:29 *368:CLK_N 0.000411513
16 *106:29 *384:D 0
17 *106:29 *384:RESET_B 0
18 *106:29 *120:58 0
19 *106:29 *145:28 7.26018e-05
20 *106:29 *153:10 0
21 *323:B *106:29 1.91246e-05
22 *340:B *106:13 2.12436e-05
23 *425:A *106:29 3.61024e-05
24 *41:33 *106:29 0.000141062
25 *51:17 *106:29 8.33134e-05
*RES
1 *364:Q *106:13 17.05
2 *106:13 *106:29 43.125
3 *106:29 *429:A 9.3
4 *106:13 *314:A_N 19.1929
*END
*D_NET *107 0.000681633
*CONN
*I *430:A I *D sky130_fd_sc_hd__buf_16
*I *321:Y O *D sky130_fd_sc_hd__o21ai_4
*CAP
1 *430:A 0.000123522
2 *321:Y 0.000123522
3 *13:66 *430:A 0.000140383
4 *32:43 *430:A 0.000156955
5 *67:10 *430:A 0.000137252
*RES
1 *321:Y *430:A 30.9036
*END
*D_NET *108 0.00362738
*CONN
*I *431:A I *D sky130_fd_sc_hd__buf_16
*I *316:X O *D sky130_fd_sc_hd__mux2_4
*CAP
1 *431:A 0.000591579
2 *316:X 0.000591579
3 *431:A *323:A_N 0.000890176
4 *431:A *439:A 0.000402381
5 *431:A *121:36 0.000664864
6 *431:A *153:10 3.21368e-06
7 *24:9 *431:A 2.99273e-05
8 *41:33 *431:A 0.000396003
9 *98:17 *431:A 5.7657e-05
*RES
1 *316:X *431:A 45.7071
*END
*D_NET *109 0.00452566
*CONN
*I *432:A I *D sky130_fd_sc_hd__buf_16
*I *362:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *432:A 0
2 *362:Q 0.000969404
3 *109:11 0.000969404
4 *109:11 *329:A_N 6.1578e-06
5 *109:11 *360:CLK_N 0.000411801
6 *109:11 *413:A 0.000216458
7 *109:11 *116:15 2.35912e-05
8 *109:11 *120:32 2.37991e-05
9 *363:SET_B *109:11 0.000489834
10 *369:SET_B *109:11 0.000350093
11 *13:66 *109:11 2.79483e-05
12 *33:18 *109:11 0.000295379
13 *42:28 *109:11 0.000693738
14 *100:22 *109:11 4.80509e-05
*RES
1 *362:Q *109:11 42.3357
2 *109:11 *432:A 9.3
*END
*D_NET *110 0.00698032
*CONN
*I *433:A I *D sky130_fd_sc_hd__buf_16
*I *363:Q O *D sky130_fd_sc_hd__dfbbn_2
*CAP
1 *433:A 0.00129025
2 *363:Q 0.00167734
3 *110:17 0.0029676
4 *110:17 *323:A_N 2.8322e-05
5 *110:17 *382:CLK 2.57986e-05
6 *110:17 *382:D 0.000111974
7 *110:17 *382:RESET_B 6.31355e-05
8 *110:17 *114:15 1.0759e-05
9 *110:17 *138:10 0.000250405
10 *326:B *433:A 6.54543e-05
11 *362:SET_B *110:17 6.93171e-05
12 *363:RESET_B *110:17 0.000104572
13 *377:CLK *433:A 4.46267e-05
14 *10:44 *433:A 1.64847e-05
15 *12:10 *433:A 0.000223599
16 *54:16 *110:17 3.06847e-05
*RES
1 *363:Q *110:17 38.7643
2 *110:17 *433:A 23.6036
*END
*D_NET *111 0.00565514
*CONN
*I *434:A I *D sky130_fd_sc_hd__buf_16
*I *387:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *434:A 0
2 *387:X 0.00135772
3 *111:8 0.00135772
4 *111:8 *370:D 0.000366928
5 *111:8 *371:D 0.000164976
6 *111:8 *379:D 0.000552468
7 *111:8 *137:13 0.000104586
8 *111:8 *147:8 8.46261e-05
9 *206:DIODE *111:8 1.33062e-05
10 *361:SET_B *111:8 0.000111152
11 *364:SET_B *111:8 8.69298e-05
12 *365:SET_B *111:8 0.000158272
13 *11:17 *111:8 0.000906818
14 *12:10 *111:8 0.000389641
*RES
1 *387:X *111:8 45.5679
2 *111:8 *434:A 13.8
*END
*D_NET *112 0.0020333
*CONN
*I *320:A1 I *D sky130_fd_sc_hd__o21ai_2
*I *420:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *320:A1 0.0003886
2 *420:X 0.0003886
3 *320:A1 *120:52 5.73775e-05
4 *195:DIODE *320:A1 0.00012136
5 *319:B *320:A1 0.000400152
6 *404:A *320:A1 0.000107425
7 *426:A *320:A1 0.000569788
*RES
1 *420:X *320:A1 38.9571
*END
*D_NET *113 0.0021234
*CONN
*I *435:A I *D sky130_fd_sc_hd__buf_16
*I *386:Q O *D sky130_fd_sc_hd__dfrtp_2
*CAP
1 *435:A 0.000197897
2 *386:Q 0.000197897
3 *435:A *361:CLK_N 6.34773e-05
4 *435:A *126:10 0.000801101
5 *1:23 *435:A 0.000803004
6 *7:11 *435:A 6.00269e-05
*RES
1 *386:Q *435:A 36.2429
*END
*D_NET *114 0.0175539
*CONN
*I *332:A I *D sky130_fd_sc_hd__or2_0
*I *342:A I *D sky130_fd_sc_hd__or2_0
*I *345:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *378:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *343:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *333:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *377:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *396:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *332:A 2.86212e-05
2 *342:A 0
3 *345:A_N 0
4 *378:RESET_B 9.61843e-05
5 *343:A_N 0.000178835
6 *333:A_N 0
7 *377:RESET_B 4.63055e-05
8 *396:X 0.000264953
9 *114:83 0.00090156
10 *114:66 0.000907353
11 *114:55 0.00119145
12 *114:33 0.0016293
13 *114:27 0.00110103
14 *114:15 0.00116403
15 *114:8 0.000467314
16 *332:A *376:RESET_B 6.08467e-05
17 *114:8 *374:D 9.19632e-06
18 *114:8 *385:CLK 0.000107496
19 *114:8 *396:A 1.65872e-05
20 *114:8 *132:6 0.000222117
21 *114:15 *410:A 1.03594e-05
22 *114:15 *132:6 0.000197685
23 *114:27 *115:14 6.81635e-05
24 *114:27 *115:16 8.82077e-05
25 *114:27 *115:20 0.000287265
26 *114:55 *370:CLK_N 0.000121494
27 *114:55 *370:D 1.41307e-05
28 *114:55 *440:A 0.000119789
29 *114:55 *116:65 7.03684e-05
30 *114:55 *116:69 0.000271602
31 *114:55 *116:75 0.000225011
32 *114:55 *116:87 0.000505277
33 *114:55 *119:29 7.04549e-06
34 *114:55 *137:13 8.60778e-05
35 *114:66 *137:13 0.000158034
36 *114:83 *386:RESET_B 4.61578e-05
37 *114:83 *440:A 0.000312422
38 *180:DIODE *114:55 0.00010462
39 *201:DIODE *114:55 0.000218651
40 *204:DIODE *114:55 6.0414e-05
41 *204:DIODE *114:66 7.4259e-05
42 *209:DIODE *114:83 0.000260325
43 *213:DIODE *114:83 0.000317072
44 *313:A *114:55 8.92089e-05
45 *313:A *114:66 0.000151258
46 *326:B *114:15 0.000142909
47 *333:B *114:55 3.98081e-06
48 *342:B *114:33 0.00063956
49 *343:B *343:A_N 0.00025527
50 *365:RESET_B *114:15 1.66398e-05
51 *365:RESET_B *114:27 0.000347266
52 *370:SET_B *343:A_N 0.000205681
53 *392:A *114:83 0.000334612
54 *2:21 *114:8 0.000219995
55 *2:21 *114:15 0.000144753
56 *6:19 *378:RESET_B 0.000185126
57 *6:19 *114:83 0.000113295
58 *6:28 *114:55 8.57749e-05
59 *6:36 *114:55 6.89158e-05
60 *8:19 *114:55 0.000124535
61 *9:35 *378:RESET_B 2.86829e-05
62 *9:35 *114:83 0.000217447
63 *9:37 *114:55 1.03594e-05
64 *10:20 *114:66 1.65872e-05
65 *10:44 *377:RESET_B 0.000106274
66 *10:44 *114:15 5.40018e-05
67 *11:41 *114:27 0.000204704
68 *12:10 *377:RESET_B 0.000257513
69 *12:10 *114:15 1.41976e-05
70 *34:21 *114:27 0
71 *39:10 *114:27 0.00025276
72 *96:5 *114:83 6.08467e-05
73 *97:5 *114:27 6.36477e-05
74 *97:5 *114:33 3.89073e-05
75 *97:19 *114:27 4.86863e-05
76 *97:36 *114:83 0.00026225
77 *98:17 *114:27 2.28961e-05
78 *98:17 *114:33 0.000737026
79 *110:17 *114:15 1.0759e-05
*RES
1 *396:X *114:8 19.55
2 *114:8 *114:15 9.14286
3 *114:15 *377:RESET_B 2.11607
4 *114:15 *114:27 29.0893
5 *114:27 *114:33 11.2143
6 *114:33 *114:55 49.4821
7 *114:55 *333:A_N 9.3
8 *114:33 *114:66 9.55357
9 *114:66 *114:83 38.1071
10 *114:83 *343:A_N 17.9429
11 *114:83 *378:RESET_B 7.05357
12 *114:66 *345:A_N 9.3
13 *114:27 *342:A 9.3
14 *114:8 *332:A 14.3357
*END
*D_NET *115 0.00944297
*CONN
*I *396:A I *D sky130_fd_sc_hd__buf_2
*I *379:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *381:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *344:A I *D sky130_fd_sc_hd__or2_0
*I *347:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *346:A I *D sky130_fd_sc_hd__or2_0
*I *380:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *397:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *396:A 0.000428654
2 *379:RESET_B 0.000238589
3 *381:RESET_B 0.000644199
4 *344:A 0.000176778
5 *347:A_N 0.000264213
6 *346:A 0
7 *380:RESET_B 1.86187e-05
8 *397:X 9.74263e-05
9 *115:29 0.000452273
10 *115:20 0.000338962
11 *115:16 0.000346424
12 *115:14 0.000688956
13 *115:5 0.000772063
14 *344:A *362:CLK_N 2.57847e-05
15 *344:A *381:D 0.000107496
16 *344:A *409:A 7.54269e-06
17 *347:A_N *367:CLK_N 0.00016697
18 *347:A_N *403:A 1.58551e-05
19 *379:RESET_B *418:A 0.000129518
20 *380:RESET_B *403:A 3.38355e-06
21 *381:RESET_B *381:D 0.000127368
22 *396:A *326:A 0.000110117
23 *396:A *374:D 5.4704e-05
24 *396:A *385:CLK 0.00030765
25 *396:A *132:6 8.38165e-05
26 *396:A *157:31 0.000329444
27 *396:A *157:40 0.000205234
28 *115:5 *383:CLK 1.82679e-05
29 *115:5 *157:28 9.94284e-06
30 *115:14 *157:28 2.61033e-05
31 *115:20 *381:D 2.02993e-05
32 *115:29 *403:A 1.78704e-05
33 *332:B *396:A 1.66626e-05
34 *344:B *344:A 6.53364e-05
35 *344:B *396:A 0.000200397
36 *360:SET_B *347:A_N 0.000190001
37 *365:RESET_B *115:14 5.71992e-05
38 *366:SET_B *379:RESET_B 0.000335932
39 *371:RESET_B *344:A 6.08467e-05
40 *372:RESET_B *347:A_N 0.00015607
41 *372:SET_B *347:A_N 8.66674e-05
42 *427:A *347:A_N 8.29571e-05
43 *10:44 *396:A 6.96846e-05
44 *11:17 *379:RESET_B 5.04829e-06
45 *11:17 *115:14 0.000132408
46 *11:17 *115:16 1.48211e-05
47 *11:33 *344:A 0.00025175
48 *11:33 *115:14 3.49076e-06
49 *11:33 *115:16 6.4937e-05
50 *11:33 *115:20 3.20264e-05
51 *11:41 *115:29 0.000125322
52 *32:43 *347:A_N 3.54435e-05
53 *32:43 *380:RESET_B 5.37479e-05
54 *32:43 *115:29 0.000157917
55 *34:21 *379:RESET_B 3.5026e-06
56 *41:33 *379:RESET_B 0.000148524
57 *97:19 *115:20 0.000210452
58 *106:13 *396:A 0.000187087
59 *114:8 *396:A 1.65872e-05
60 *114:27 *115:14 6.81635e-05
61 *114:27 *115:16 8.82077e-05
62 *114:27 *115:20 0.000287265
*RES
1 *397:X *115:5 10.6571
2 *115:5 *115:14 9.17857
3 *115:14 *115:16 1.33929
4 *115:16 *115:20 8.57143
5 *115:20 *380:RESET_B 0.473214
6 *115:20 *115:29 4.25
7 *115:29 *346:A 9.3
8 *115:29 *347:A_N 25.4607
9 *115:16 *344:A 18.05
10 *115:14 *381:RESET_B 9.63393
11 *381:RESET_B *379:RESET_B 14.9732
12 *115:5 *396:A 29.7107
*END
*D_NET *116 0.0256043
*CONN
*I *334:A I *D sky130_fd_sc_hd__or2_0
*I *324:A I *D sky130_fd_sc_hd__or2_0
*I *207:DIODE I *D sky130_fd_sc_hd__diode_2
*I *331:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *325:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *335:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *185:DIODE I *D sky130_fd_sc_hd__diode_2
*I *193:DIODE I *D sky130_fd_sc_hd__diode_2
*I *191:DIODE I *D sky130_fd_sc_hd__diode_2
*I *179:DIODE I *D sky130_fd_sc_hd__diode_2
*I *187:DIODE I *D sky130_fd_sc_hd__diode_2
*I *177:DIODE I *D sky130_fd_sc_hd__diode_2
*I *330:A I *D sky130_fd_sc_hd__or2_0
*I *376:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *398:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *334:A 0
2 *324:A 0
3 *207:DIODE 0
4 *331:A_N 0.000129716
5 *325:A_N 0
6 *335:A_N 0
7 *185:DIODE 0.00058495
8 *193:DIODE 0
9 *191:DIODE 0
10 *179:DIODE 0
11 *187:DIODE 0
12 *177:DIODE 0
13 *330:A 0
14 *376:RESET_B 0.000793867
15 *398:X 0.00101391
16 *116:124 0.000184609
17 *116:97 0.000638902
18 *116:91 0.000322829
19 *116:87 0.000580652
20 *116:75 0.000432762
21 *116:69 0.000358992
22 *116:65 0.00059536
23 *116:53 0.002107
24 *116:48 0.00229886
25 *116:43 0.00078228
26 *116:39 0.000705492
27 *116:25 0.000723578
28 *116:15 0.00211382
29 *376:RESET_B *326:A 4.13064e-05
30 *376:RESET_B *384:CLK 6.11872e-05
31 *376:RESET_B *415:A 0.000359836
32 *376:RESET_B *143:10 7.67734e-06
33 *116:15 *360:CLK_N 3.51505e-05
34 *116:39 *141:16 0.000721045
35 *116:48 *351:A 0.00021661
36 *116:48 *158:24 0.000496078
37 *116:53 *158:10 0.000252128
38 *116:53 *158:17 0.000549196
39 *116:53 *158:24 0.000263436
40 serial_data_out *116:15 0.000558167
41 *175:DIODE *116:48 3.70431e-05
42 *186:DIODE *185:DIODE 1.00901e-05
43 *200:DIODE *185:DIODE 0.000114271
44 *204:DIODE *116:91 0.000108704
45 *313:A *116:91 6.64392e-05
46 *324:B *116:43 0.00015901
47 *325:B *116:65 0
48 *325:B *116:69 0
49 *330:B *116:39 0.00124986
50 *330:B *116:43 0.000348103
51 *332:A *376:RESET_B 6.08467e-05
52 *332:B *376:RESET_B 6.08467e-05
53 *333:B *116:65 6.46815e-05
54 *333:B *116:69 2.52287e-06
55 *352:A *116:53 4.11616e-05
56 *361:RESET_B *116:48 6.27782e-05
57 *364:RESET_B *116:39 7.19065e-05
58 *364:SET_B *376:RESET_B 3.99387e-05
59 *365:RESET_B *376:RESET_B 1.03403e-05
60 *389:A *116:39 4.78069e-06
61 *389:A *116:43 1.1718e-05
62 *1:5 *116:48 0.000179614
63 *1:23 *116:15 0.00034853
64 *1:45 *116:15 0.000326505
65 *3:22 *376:RESET_B 0.000340811
66 *3:22 *116:25 0
67 *4:9 *376:RESET_B 0.000207134
68 *4:9 *116:25 0.000388109
69 *4:9 *116:39 5.33048e-05
70 *4:21 *376:RESET_B 8.18541e-05
71 *4:22 *185:DIODE 0.000151001
72 *5:16 *116:43 0.000621616
73 *5:16 *116:48 3.52873e-06
74 *5:29 *116:43 6.08467e-05
75 *6:19 *116:43 0.000209636
76 *6:28 *116:65 1.63255e-05
77 *7:11 *116:43 0.000134717
78 *8:19 *116:87 0.000130755
79 *11:17 *376:RESET_B 0.000108543
80 *33:18 *116:15 0.000100487
81 *33:18 *116:39 2.57986e-05
82 *38:8 *116:15 0.000285574
83 *63:10 *185:DIODE 1.43832e-05
84 *63:10 *116:91 2.41827e-05
85 *63:10 *116:97 2.44599e-05
86 *100:22 *116:15 0.000216304
87 *109:11 *116:15 2.35912e-05
88 *114:55 *116:65 7.03684e-05
89 *114:55 *116:69 0.000271602
90 *114:55 *116:75 0.000225011
91 *114:55 *116:87 0.000505277
*RES
1 *398:X *116:15 27.3379
2 *116:15 *376:RESET_B 20.7679
3 *116:15 *116:25 5.74107
4 *116:25 *330:A 13.8
5 *116:25 *116:39 17.4107
6 *116:39 *116:43 11.2321
7 *116:43 *116:48 17.2143
8 *116:48 *116:53 42
9 *116:53 *177:DIODE 9.3
10 *116:53 *116:65 5.51786
11 *116:65 *116:69 3.32143
12 *116:69 *187:DIODE 9.3
13 *116:69 *116:75 1.76786
14 *116:75 *179:DIODE 9.3
15 *116:75 *116:87 16.0714
16 *116:87 *116:91 5.07143
17 *116:91 *191:DIODE 9.3
18 *116:91 *116:97 0.946429
19 *116:97 *193:DIODE 9.3
20 *116:97 *185:DIODE 26.9607
21 *116:87 *335:A_N 9.3
22 *116:65 *325:A_N 9.3
23 *116:48 *116:124 5.03571
24 *116:124 *331:A_N 11.3893
25 *116:124 *207:DIODE 9.3
26 *116:43 *324:A 9.3
27 *116:39 *334:A 9.3
*END
*D_NET *117 0.0139952
*CONN
*I *398:A I *D sky130_fd_sc_hd__buf_2
*I *375:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *374:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *373:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *323:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *399:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *398:A 0.000449054
2 *375:RESET_B 3.37814e-05
3 *374:RESET_B 0.00017785
4 *373:RESET_B 0.00197395
5 *323:A_N 0.000969973
6 *399:X 0
7 *117:39 0.00120692
8 *117:8 0.00212369
9 *117:4 0.000624101
10 *323:A_N *322:A 7.96718e-05
11 *323:A_N *326:A 0.000151913
12 *323:A_N *384:CLK 5.01846e-05
13 *323:A_N *384:D 5.46207e-05
14 *323:A_N *399:A 6.74713e-05
15 *323:A_N *118:42 5.1493e-06
16 *323:A_N *120:18 0.000471811
17 *323:A_N *120:58 0.000221277
18 *323:A_N *121:36 2.81681e-05
19 *323:A_N *153:10 4.15414e-05
20 *373:RESET_B *368:D 0.00011813
21 *373:RESET_B *373:D 0.000251507
22 *373:RESET_B *145:28 0.000201656
23 *373:RESET_B *164:16 0.000537864
24 *374:RESET_B *364:CLK_N 8.4771e-05
25 *374:RESET_B *386:RESET_B 0.000250495
26 *375:RESET_B *366:D 1.99581e-05
27 *375:RESET_B *129:15 0.000102546
28 *398:A *360:CLK_N 0.000353661
29 *117:8 *322:A 1.8234e-05
30 *117:8 *360:CLK_N 0.000157107
31 *117:39 *373:D 3.38116e-06
32 *117:39 *386:RESET_B 0.000192514
33 *117:39 *126:10 0.000375493
34 *183:DIODE *374:RESET_B 5.58964e-05
35 *205:DIODE *323:A_N 1.88333e-05
36 *362:SET_B *323:A_N 5.21049e-05
37 *364:RESET_B *373:RESET_B 0.000105882
38 *367:SET_B *323:A_N 0.00054154
39 *388:TE_B *323:A_N 0.000159908
40 *431:A *323:A_N 0.000890176
41 *2:21 *373:RESET_B 5.79479e-06
42 *34:16 *323:A_N 0.000130534
43 *34:16 *117:8 2.12358e-05
44 *38:8 *374:RESET_B 0.000250495
45 *38:8 *117:39 0.000153468
46 *98:17 *323:A_N 6.27782e-05
47 *99:14 *373:RESET_B 2.47178e-05
48 *100:22 *398:A 9.50413e-05
49 *110:17 *323:A_N 2.8322e-05
*RES
1 *399:X *117:4 9.3
2 *117:4 *117:8 6.89286
3 *117:8 *323:A_N 40.175
4 *117:8 *373:RESET_B 29.4375
5 *373:RESET_B *117:39 17.7946
6 *117:39 *374:RESET_B 9.66964
7 *117:39 *375:RESET_B 5.38393
8 *117:4 *398:A 15.0857
*END
*D_NET *118 0.0131712
*CONN
*I *338:A I *D sky130_fd_sc_hd__or2_0
*I *340:A I *D sky130_fd_sc_hd__or2_0
*I *322:A I *D sky130_fd_sc_hd__or2_0
*I *385:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *384:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *328:A I *D sky130_fd_sc_hd__or2_0
*I *339:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *400:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *338:A 0.000544372
2 *340:A 0.000168884
3 *322:A 0.000534274
4 *385:RESET_B 0
5 *384:RESET_B 0.000147352
6 *328:A 0.000231195
7 *339:A_N 0.000422305
8 *400:X 0.000322598
9 *118:70 0.000838347
10 *118:42 0.000189393
11 *118:41 0.00117699
12 *118:28 0.00102817
13 *118:19 0.00149831
14 *118:8 0.00170961
15 *322:A *369:CLK_N 0.000213449
16 *322:A *369:D 6.36477e-05
17 *322:A *386:D 0.000261379
18 *384:RESET_B *312:A 8.35355e-06
19 *384:RESET_B *326:A 0.00012398
20 *384:RESET_B *384:CLK 0.000259643
21 *384:RESET_B *384:D 9.33587e-05
22 *384:RESET_B *120:58 8.36586e-06
23 *118:19 *120:52 7.28994e-06
24 *118:41 *326:A 6.08467e-05
25 *118:41 *329:A_N 6.08467e-05
26 *118:42 *326:A 2.99273e-05
27 pad_gpio_dm[0] *118:8 0.000301947
28 pad_gpio_inenb *339:A_N 6.59359e-06
29 pad_gpio_outenb *118:19 0
30 *314:A_N *118:41 0.000222225
31 *320:B1 *339:A_N 7.45746e-05
32 *323:A_N *322:A 7.96718e-05
33 *323:A_N *118:42 5.1493e-06
34 *329:B *118:41 8.93246e-05
35 *339:B *339:A_N 9.9774e-06
36 *340:B *118:41 0.000265786
37 *360:RESET_B *322:A 0
38 *368:RESET_B *338:A 6.27782e-05
39 *368:RESET_B *340:A 6.08467e-05
40 *369:RESET_B *338:A 0
41 *1:45 *322:A 0
42 *2:38 *118:8 0.000300318
43 *2:38 *118:19 0.00116145
44 *30:8 *338:A 0.000187307
45 *30:8 *118:28 0
46 *34:16 *322:A 8.58461e-05
47 *35:13 *339:A_N 4.89072e-05
48 *39:16 *118:19 0
49 *81:10 *118:19 0
50 *81:10 *118:28 0
51 *81:10 *118:41 7.78924e-05
52 *99:14 *340:A 0.000109427
53 *100:22 *338:A 0
54 *106:29 *384:RESET_B 0
55 *117:8 *322:A 1.8234e-05
*RES
1 *400:X *118:8 20.1571
2 *118:8 *339:A_N 20.4071
3 *118:8 *118:19 22.2857
4 *118:19 *328:A 17.2107
5 *118:19 *118:28 5.28571
6 *118:28 *118:41 21.625
7 *118:41 *118:42 0.732143
8 *118:42 *384:RESET_B 8.5625
9 *118:42 *385:RESET_B 4.5
10 *118:41 *322:A 25.2821
11 *118:28 *118:70 2.25
12 *118:70 *340:A 17.2107
13 *118:70 *338:A 24.6214
*END
*D_NET *119 0.0137589
*CONN
*I *387:A I *D sky130_fd_sc_hd__buf_2
*I *386:RESET_B I *D sky130_fd_sc_hd__dfrtp_2
*I *341:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *401:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *387:A 3.00688e-05
2 *386:RESET_B 0.00112152
3 *341:A_N 0.000157743
4 *401:X 0
5 *119:29 0.00281459
6 *119:5 0.00182075
7 *341:A_N *400:A 0.00028932
8 *341:A_N *439:A 3.34603e-05
9 *386:RESET_B *361:CLK_N 0.000137259
10 *119:29 *370:D 6.54273e-05
11 *119:29 *400:A 3.29097e-05
12 *119:29 *436:A 8.65796e-05
13 *119:29 *439:A 4.19841e-05
14 *119:29 *145:17 0.000607811
15 *184:DIODE *341:A_N 0.000250197
16 *201:DIODE *119:29 0.000132675
17 *206:DIODE *386:RESET_B 4.24488e-05
18 *206:DIODE *387:A 1.65872e-05
19 *209:DIODE *386:RESET_B 5.00525e-05
20 *339:B *119:29 0.00113671
21 *361:RESET_B *386:RESET_B 0.000307892
22 *370:RESET_B *119:29 0.000145794
23 *374:RESET_B *386:RESET_B 0.000250495
24 *427:A *119:29 6.46815e-05
25 *8:11 *386:RESET_B 0.000749588
26 *8:19 *386:RESET_B 0.000914308
27 *8:19 *119:29 0.000617015
28 *9:35 *386:RESET_B 0.000204112
29 *9:35 *119:29 0.000418562
30 *9:37 *119:29 6.23012e-05
31 *35:13 *119:29 0.000144381
32 *38:8 *386:RESET_B 8.15182e-05
33 *96:25 *386:RESET_B 0.000194842
34 *96:34 *386:RESET_B 0.000153477
35 *96:41 *386:RESET_B 0.00014603
36 *96:56 *386:RESET_B 0.000190134
37 *114:55 *119:29 7.04549e-06
38 *114:83 *386:RESET_B 4.61578e-05
39 *117:39 *386:RESET_B 0.000192514
*RES
1 *401:X *119:5 13.8
2 *119:5 *341:A_N 18.5321
3 *119:5 *119:29 46.2321
4 *119:29 *386:RESET_B 40.7054
5 *119:29 *387:A 9.83571
*END
*D_NET *120 0.0152112
*CONN
*I *326:A I *D sky130_fd_sc_hd__or2_0
*I *329:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *327:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *336:A I *D sky130_fd_sc_hd__or2_0
*I *337:A_N I *D sky130_fd_sc_hd__nand2b_2
*I *383:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *382:RESET_B I *D sky130_fd_sc_hd__dfrtp_4
*I *402:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *326:A 0.000890773
2 *329:A_N 0.000209229
3 *327:A_N 2.15683e-05
4 *336:A 0
5 *337:A_N 0
6 *383:RESET_B 0.000163844
7 *382:RESET_B 8.03551e-05
8 *402:X 0.000164254
9 *120:61 0.000423712
10 *120:58 0.00121206
11 *120:52 0.00119477
12 *120:32 0.00184105
13 *120:18 0.00100182
14 *120:15 0.000320082
15 *120:7 0.000244609
16 *326:A *384:CLK 1.40736e-05
17 *326:A *385:D 9.12416e-06
18 *326:A *132:6 0.000116462
19 *326:A *145:28 0.000246428
20 *327:A_N *312:A 4.31603e-06
21 *329:A_N *312:A 1.58551e-05
22 *329:A_N *360:CLK_N 0.000112837
23 *382:RESET_B *138:10 0.000107496
24 *383:RESET_B *384:D 9.37259e-05
25 *120:7 *406:A 0.00015888
26 *120:7 *138:10 1.56049e-05
27 *120:18 *384:D 0.000471811
28 *120:58 *384:D 0.000169659
29 *120:61 *312:A 8.58641e-05
30 *120:61 *384:CLK 0.000107496
31 *176:DIODE *120:52 3.99086e-06
32 *195:DIODE *120:52 2.86829e-05
33 *314:A_N *326:A 7.31578e-05
34 *314:A_N *329:A_N 2.16355e-05
35 *315:B *120:52 0.000107496
36 *318:C *120:52 0.000203317
37 *320:A1 *120:52 5.73775e-05
38 *323:A_N *326:A 0.000151913
39 *323:A_N *120:18 0.000471811
40 *323:A_N *120:58 0.000221277
41 *332:B *326:A 2.16355e-05
42 *340:B *326:A 0.000227378
43 *360:SET_B *326:A 9.87116e-05
44 *362:SET_B *120:32 0.000147046
45 *367:SET_B *383:RESET_B 4.28856e-07
46 *367:SET_B *120:32 3.02761e-06
47 *376:RESET_B *326:A 4.13064e-05
48 *384:RESET_B *326:A 0.00012398
49 *384:RESET_B *120:58 8.36586e-06
50 *396:A *326:A 0.000110117
51 *426:A *120:52 0.00107407
52 *2:26 *120:32 0.000154145
53 *2:26 *120:52 9.52298e-05
54 *2:38 *120:52 0.00083912
55 *13:66 *120:32 8.85135e-05
56 *33:18 *329:A_N 0.00013147
57 *36:8 *120:52 3.74005e-05
58 *42:28 *329:A_N 6.27782e-05
59 *54:16 *382:RESET_B 2.57494e-05
60 *81:10 *120:52 0.000271402
61 *101:8 *120:52 0.000467997
62 *106:13 *326:A 9.08935e-05
63 *106:29 *120:58 0
64 *109:11 *329:A_N 6.1578e-06
65 *109:11 *120:32 2.37991e-05
66 *110:17 *382:RESET_B 6.31355e-05
67 *118:19 *120:52 7.28994e-06
68 *118:41 *326:A 6.08467e-05
69 *118:41 *329:A_N 6.08467e-05
70 *118:42 *326:A 2.99273e-05
*RES
1 *402:X *120:7 12.2107
2 *120:7 *382:RESET_B 2.11607
3 *120:7 *120:15 4.5
4 *120:15 *120:18 11
5 *120:18 *383:RESET_B 11.2857
6 *120:18 *120:32 8.375
7 *120:32 *337:A_N 9.3
8 *120:32 *120:52 48.875
9 *120:52 *336:A 9.3
10 *120:15 *120:58 3.16071
11 *120:58 *120:61 7.91071
12 *120:61 *327:A_N 9.72857
13 *120:61 *329:A_N 22.55
14 *120:58 *326:A 48.8536
*END
*D_NET *121 0.0123167
*CONN
*I *402:A I *D sky130_fd_sc_hd__buf_2
*I *399:A I *D sky130_fd_sc_hd__buf_2
*I *397:A I *D sky130_fd_sc_hd__buf_2
*I *401:A I *D sky130_fd_sc_hd__buf_2
*I *400:A I *D sky130_fd_sc_hd__buf_2
*I *403:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *402:A 0
2 *399:A 0.000487252
3 *397:A 0.000837719
4 *401:A 1.81453e-05
5 *400:A 0.00041328
6 *403:X 0.000762759
7 *121:51 0.000779821
8 *121:36 0.00154799
9 *121:8 0.000694968
10 *121:7 0.001444
11 *397:A *383:CLK 1.54322e-05
12 *397:A *383:D 2.16355e-05
13 *399:A *360:CLK_N 0.000111802
14 *399:A *384:CLK 6.11447e-06
15 *399:A *162:8 0.000124362
16 *400:A *439:A 1.07549e-05
17 *121:7 *388:A 3.15902e-05
18 *121:7 *439:A 1.56911e-05
19 *121:8 *439:A 0.000177473
20 *121:36 *407:A 1.32845e-05
21 *121:36 *439:A 4.39194e-05
22 *121:51 *406:A 0.000154145
23 *121:51 *138:10 0.00015607
24 pad_gpio_dm[0] *400:A 0.000310253
25 *319:A_N *400:A 6.36477e-05
26 *319:B *400:A 6.55312e-05
27 *323:A_N *399:A 6.74713e-05
28 *323:A_N *121:36 2.81681e-05
29 *327:B *399:A 5.84021e-05
30 *339:B *401:A 2.52984e-05
31 *341:A_N *400:A 0.00028932
32 *341:B *400:A 0.000117376
33 *362:SET_B *399:A 0.000130079
34 *362:SET_B *121:36 0.000205476
35 *362:SET_B *121:51 2.57465e-06
36 *369:SET_B *400:A 9.87169e-05
37 *431:A *121:36 0.000664864
38 *13:66 *121:8 0.000435416
39 *13:66 *121:36 0.000313879
40 *34:16 *399:A 0.000485144
41 *35:13 *401:A 2.49791e-05
42 *41:33 *397:A 0.00018628
43 *41:33 *121:51 5.39247e-05
44 *51:17 *121:7 5.73753e-05
45 *54:16 *121:36 1.07403e-05
46 *54:16 *121:51 0.000272378
47 *67:10 *399:A 3.08084e-05
48 *67:10 *400:A 1.3262e-05
49 *67:10 *121:8 3.42037e-06
50 *67:10 *121:51 0.000284801
51 *69:8 *400:A 7.14062e-05
52 *100:22 *399:A 4.45999e-05
53 *119:29 *400:A 3.29097e-05
*RES
1 *403:X *121:7 21.7286
2 *121:7 *121:8 6.5
3 *121:8 *400:A 24.4964
4 *121:8 *401:A 14.3357
5 *121:7 *121:36 16.9286
6 *121:36 *397:A 18.675
7 *121:36 *121:51 15.7857
8 *121:51 *399:A 29.7464
9 *121:51 *402:A 9.3
*END
*D_NET *122 0.00454794
*CONN
*I *360:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *312:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *360:CLK_N 0.00144123
2 *312:Y 0.00144123
3 *360:CLK_N *360:D 4.23858e-05
4 *360:CLK_N *412:A 8.4946e-05
5 *329:A_N *360:CLK_N 0.000112837
6 *329:B *360:CLK_N 1.5714e-05
7 *360:RESET_B *360:CLK_N 6.96754e-05
8 *398:A *360:CLK_N 0.000353661
9 *399:A *360:CLK_N 0.000111802
10 *33:18 *360:CLK_N 9.87472e-05
11 *100:22 *360:CLK_N 0.000171651
12 *109:11 *360:CLK_N 0.000411801
13 *116:15 *360:CLK_N 3.51505e-05
14 *117:8 *360:CLK_N 0.000157107
*RES
1 *312:Y *360:CLK_N 49.9929
*END
*D_NET *123 0.00861268
*CONN
*I *388:A I *D sky130_fd_sc_hd__ebufn_8
*I *311:A I *D sky130_fd_sc_hd__inv_2
*I *421:X O *D sky130_fd_sc_hd__buf_2
*CAP
1 *388:A 0.0014588
2 *311:A 0.000696498
3 *421:X 0.000159167
4 *123:8 0.00231446
5 *388:A *417:A 8.69237e-05
6 *388:A *439:A 0.000441308
7 *388:A *146:11 6.3657e-05
8 pad_gpio_out *123:8 5.89592e-05
9 *195:DIODE *311:A 0.000114271
10 *212:DIODE *311:A 0.00146885
11 *212:DIODE *123:8 6.09513e-05
12 *367:RESET_B *311:A 8.34211e-06
13 *388:TE_B *388:A 4.7457e-05
14 *425:A *311:A 8.91694e-05
15 *425:A *123:8 6.93171e-05
16 *18:5 *311:A 5.31465e-05
17 *42:28 *311:A 0.00130399
18 *51:17 *388:A 8.58199e-05
19 *121:7 *388:A 3.15902e-05
*RES
1 *421:X *123:8 16.1929
2 *123:8 *311:A 35.7464
3 *123:8 *388:A 30.925
*END
*D_NET *124 0.00350564
*CONN
*I *361:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *348:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *361:CLK_N 0.00086153
2 *348:Y 0.00086153
3 *361:CLK_N *351:A 1.22289e-05
4 *361:CLK_N *364:CLK_N 0.000520969
5 *361:CLK_N *386:D 0.000145255
6 *361:CLK_N *129:15 0.000556896
7 *361:CLK_N *137:13 3.00829e-05
8 *361:CLK_N *158:24 0.000141399
9 *361:RESET_B *361:CLK_N 0.000175018
10 *386:RESET_B *361:CLK_N 0.000137259
11 *435:A *361:CLK_N 6.34773e-05
*RES
1 *348:Y *361:CLK_N 49.6357
*END
*D_NET *125 0.0011538
*CONN
*I *362:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *349:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *362:CLK_N 0.000212462
2 *349:Y 0.000212462
3 *362:CLK_N *409:A 0.000109427
4 *362:CLK_N *158:70 0.00028688
5 *344:A *362:CLK_N 2.57847e-05
6 *349:A *362:CLK_N 0.00028688
7 *371:RESET_B *362:CLK_N 1.9898e-05
*RES
1 *349:Y *362:CLK_N 33.4393
*END
*D_NET *126 0.00763883
*CONN
*I *363:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *350:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *363:CLK_N 0.000495556
2 *350:Y 0.00114709
3 *126:10 0.00164264
4 *363:CLK_N *368:CLK_N 6.27718e-05
5 *363:CLK_N *383:D 2.29454e-05
6 *363:CLK_N *410:A 6.08467e-05
7 *363:CLK_N *418:A 4.23858e-05
8 *363:CLK_N *158:70 0.000536223
9 *126:10 *373:CLK 6.08467e-05
10 *126:10 *373:D 0.000105778
11 *366:RESET_B *126:10 0.000171988
12 *366:SET_B *126:10 6.47907e-05
13 *435:A *126:10 0.000801101
14 *1:23 *126:10 0.000131351
15 *3:22 *363:CLK_N 0.000304129
16 *11:17 *363:CLK_N 0.000451209
17 *11:17 *126:10 0.000103688
18 *13:9 *126:10 7.63961e-05
19 *34:21 *126:10 0.000856009
20 *41:33 *363:CLK_N 0.00012559
21 *117:39 *126:10 0.000375493
*RES
1 *350:Y *126:10 46.4071
2 *126:10 *363:CLK_N 21.3536
*END
*D_NET *127 0.00287271
*CONN
*I *364:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *351:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *364:CLK_N 0.000710713
2 *351:Y 0.000710713
3 *364:CLK_N *351:A 0.000176652
4 *364:CLK_N *374:D 9.44796e-05
5 *364:CLK_N *414:A 0.000100956
6 *364:CLK_N *158:24 0.000358287
7 *183:DIODE *364:CLK_N 0.000115167
8 *361:CLK_N *364:CLK_N 0.000520969
9 *374:RESET_B *364:CLK_N 8.4771e-05
*RES
1 *351:Y *364:CLK_N 44.7964
*END
*D_NET *128 0.00343207
*CONN
*I *365:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *352:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *365:CLK_N 0.00109099
2 *352:Y 0.00109099
3 *365:CLK_N *371:CLK_N 6.65668e-05
4 *365:CLK_N *373:CLK 5.4704e-05
5 *365:CLK_N *440:A 0.000231561
6 *365:CLK_N *157:21 0.000173028
7 *213:DIODE *365:CLK_N 0.000254031
8 *391:A *365:CLK_N 0.000208621
9 *5:29 *365:CLK_N 7.5848e-05
10 *9:14 *365:CLK_N 0.000180676
11 *32:43 *365:CLK_N 5.04829e-06
*RES
1 *352:Y *365:CLK_N 43.6714
*END
*D_NET *129 0.00425806
*CONN
*I *366:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *353:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *366:CLK_N 0
2 *353:Y 0.00138394
3 *129:15 0.00138394
4 *129:15 *366:D 0.000145269
5 *129:15 *375:D 9.46172e-05
6 *129:15 *158:10 3.44412e-06
7 *129:15 *158:17 0.000132509
8 *129:15 *158:24 2.50929e-05
9 *129:15 *164:16 4.14268e-05
10 *173:DIODE *129:15 5.27224e-05
11 *361:CLK_N *129:15 0.000556896
12 *375:CLK *129:15 6.12919e-06
13 *375:RESET_B *129:15 0.000102546
14 *7:11 *129:15 0.000115134
15 *7:19 *129:15 0.000214397
*RES
1 *353:Y *129:15 44.5679
2 *129:15 *366:CLK_N 9.3
*END
*D_NET *130 0.00160193
*CONN
*I *367:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *354:Y O *D sky130_fd_sc_hd__inv_2
*CAP
1 *367:CLK_N 0.000394562
2 *354:Y 0.000394562
3 *367:CLK_N *145:28 7.17478e-05
4 pad_gpio_dm[1] *367:CLK_N 1.66771e-05
5 *347:A_N *367:CLK_N 0.00016697
6 *370:RESET_B *367:CLK_N 2.16355e-05
7 *372:SET_B *367:CLK_N 0.000141811
8 *427:A *367:CLK_N 3.67457e-05
9 *14:12 *367:CLK_N 0.000236198
10 *98:17 *367:CLK_N 0.000121018
*RES
1 *354:Y *367:CLK_N 37.3321
*END
*D_NET *131 0.00204782
*CONN
*I *368:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *355:Y O *D sky130_fd_sc_hd__inv_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *368:CLK_N 0.000465468
2 *355:Y 0.000465468
3 *368:CLK_N *362:D 1.03594e-05
4 *368:CLK_N *368:D 0.00016195
5 *368:CLK_N *382:D 0.000141062
6 *368:CLK_N *145:28 0.000246085
7 *363:CLK_N *368:CLK_N 6.27718e-05
8 *1:45 *368:CLK_N 4.34701e-05
9 *99:14 *368:CLK_N 3.96696e-05
10 *106:29 *368:CLK_N 0.000411513
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *355:Y *368:CLK_N 38.4214
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *132 0.0080727
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *369:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *356:Y O *D sky130_fd_sc_hd__inv_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *369:CLK_N 0.00020861
2 *356:Y 0.00122018
3 *132:6 0.00142879
4 *369:CLK_N *386:D 5.24474e-05
5 *369:CLK_N *140:8 0.000161243
6 *132:6 *374:D 0.000398557
7 *132:6 *381:D 0.000155293
8 *132:6 *410:A 2.75892e-05
9 *132:6 *417:A 1.80303e-05
10 *132:6 *140:8 0.000169858
11 *132:6 *146:11 0.000311769
12 *132:6 *158:51 0.00095192
13 *322:A *369:CLK_N 0.000213449
14 *326:A *132:6 0.000116462
15 *332:B *132:6 1.66626e-05
16 *344:B *132:6 0.000417827
17 *370:RESET_B *132:6 0.000134976
18 *396:A *132:6 8.38165e-05
19 *428:A *132:6 0.000122893
20 *2:21 *132:6 0.000361808
21 *3:22 *132:6 8.70662e-06
22 *10:44 *132:6 6.23012e-05
23 *11:17 *132:6 0.000397123
24 *11:33 *132:6 1.18339e-05
25 *11:58 *132:6 7.22987e-05
26 *34:16 *369:CLK_N 0.000391616
27 *97:19 *132:6 3.01773e-05
28 *104:7 *369:CLK_N 0.000106653
29 *114:8 *132:6 0.000222117
30 *114:15 *132:6 0.000197685
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *356:Y *132:6 49.7464
2 *132:6 *369:CLK_N 21.3179
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *133 0.00253521
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *370:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *357:Y O *D sky130_fd_sc_hd__inv_2
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *370:CLK_N 0.000681877
2 *357:Y 0.000681877
3 *370:CLK_N *440:A 0.000113237
4 *201:DIODE *370:CLK_N 0.000936729
5 *114:55 *370:CLK_N 0.000121494
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *357:Y *370:CLK_N 37.1714
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *134 0.00322837
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *403:A I *D sky130_fd_sc_hd__buf_2
*I *422:X O *D sky130_fd_sc_hd__buf_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *403:A 0.00124206
2 *422:X 0.00124206
3 *403:A *380:D 5.20546e-06
4 *347:A_N *403:A 1.58551e-05
5 *380:CLK *403:A 1.65872e-05
6 *380:RESET_B *403:A 3.38355e-06
7 *427:A *403:A 0.000143295
8 *4:21 *403:A 0.000143295
9 *11:41 *403:A 0.000343552
10 *32:43 *403:A 3.35651e-05
11 *96:5 *403:A 2.16355e-05
12 *115:29 *403:A 1.78704e-05
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *422:X *403:A 41.9929
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *135 0.00437898
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *371:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *358:Y O *D sky130_fd_sc_hd__inv_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *371:CLK_N 0.00111408
2 *358:Y 0.00111408
3 *371:CLK_N *440:A 0.000378093
4 *371:CLK_N *158:10 0.000210531
5 *371:CLK_N *158:46 0.000380352
6 *204:DIODE *371:CLK_N 0.000110297
7 *365:CLK_N *371:CLK_N 6.65668e-05
8 *371:SET_B *371:CLK_N 7.13972e-05
9 *5:29 *371:CLK_N 0.000462422
10 *9:35 *371:CLK_N 0.000410308
11 *10:20 *371:CLK_N 6.08467e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *358:Y *371:CLK_N 46.2607
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *136 0.000752239
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *372:CLK_N I *D sky130_fd_sc_hd__dfbbn_2
*I *359:Y O *D sky130_fd_sc_hd__inv_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *372:CLK_N 0.000139653
2 *359:Y 0.000139653
3 *372:CLK_N *418:A 0.000161243
4 *372:CLK_N *158:46 0.000101887
5 *97:24 *372:CLK_N 0.000209802
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *359:Y *372:CLK_N 22.8321
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *137 0.00821837
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *386:CLK I *D sky130_fd_sc_hd__dfrtp_2
*I *313:Y O *D sky130_fd_sc_hd__inv_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *386:CLK 0
2 *313:Y 0
3 *137:13 0.00153033
4 *137:5 0.00153033
5 *137:13 *365:D 5.46907e-05
6 *137:13 *370:D 0.000985958
7 *137:13 *379:D 0.000545452
8 *137:13 *386:D 8.95662e-05
9 *137:13 *151:8 6.65668e-05
10 *313:A *137:13 0.000240136
11 *361:CLK_N *137:13 3.00829e-05
12 *361:RESET_B *137:13 0.000143668
13 *10:7 *137:13 0.000901863
14 *10:20 *137:13 0.0010162
15 *11:17 *137:13 0.000734827
16 *111:8 *137:13 0.000104586
17 *114:55 *137:13 8.60778e-05
18 *114:66 *137:13 0.000158034
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *313:Y *137:5 13.8
2 *137:5 *137:13 48.9643
3 *137:13 *386:CLK 9.3
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *138 0.00279757
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *363:D I *D sky130_fd_sc_hd__dfbbn_2
*I *383:D I *D sky130_fd_sc_hd__dfrtp_4
*I *406:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *363:D 0
2 *383:D 0.000296702
3 *406:X 0.000285915
4 *138:10 0.000582617
5 *383:D *145:28 0.000154819
6 *383:D *158:70 0.000253215
7 *138:10 *384:D 0.000135664
8 *138:10 *406:A 5.6238e-05
9 *363:CLK_N *383:D 2.29454e-05
10 *382:RESET_B *138:10 0.000107496
11 *397:A *383:D 2.16355e-05
12 *3:22 *383:D 0.000158244
13 *41:33 *383:D 0.000299994
14 *110:17 *138:10 0.000250405
15 *120:7 *138:10 1.56049e-05
16 *121:51 *138:10 0.00015607
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *406:X *138:10 24.4786
2 *138:10 *383:D 25.7464
3 *138:10 *363:D 9.3
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *139 0.000861768
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *368:D I *D sky130_fd_sc_hd__dfbbn_2
*I *385:D I *D sky130_fd_sc_hd__dfrtp_4
*I *411:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *368:D 4.89521e-05
2 *385:D 0.000109104
3 *411:X 0
4 *139:4 0.000158056
5 *368:D *145:28 1.88563e-05
6 *385:D *145:28 4.54854e-05
7 *326:A *385:D 9.12416e-06
8 *360:SET_B *385:D 0.00018014
9 *368:CLK_N *368:D 0.00016195
10 *373:RESET_B *368:D 0.00011813
11 *1:45 *385:D 0
12 *99:14 *368:D 1.19705e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *411:X *139:4 9.3
2 *139:4 *385:D 20.8536
3 *139:4 *368:D 11.4786
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *140 0.00473756
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *360:D I *D sky130_fd_sc_hd__dfbbn_2
*I *374:D I *D sky130_fd_sc_hd__dfrtp_4
*I *412:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *360:D 2.9191e-05
2 *374:D 0.00143878
3 *412:X 0.00011789
4 *140:8 0.00158586
5 *360:D *412:A 0.000110306
6 *374:D *364:D 2.16355e-05
7 *374:D *385:CLK 9.62217e-06
8 *374:D *411:A 3.12402e-05
9 *360:CLK_N *360:D 4.23858e-05
10 *364:CLK_N *374:D 9.44796e-05
11 *369:CLK_N *140:8 0.000161243
12 *396:A *374:D 5.4704e-05
13 *3:22 *374:D 0.00013408
14 *3:22 *140:8 0.000167294
15 *104:7 *140:8 0.000161243
16 *114:8 *374:D 9.19632e-06
17 *132:6 *374:D 0.000398557
18 *132:6 *140:8 0.000169858
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *412:X *140:8 17.7107
2 *140:8 *374:D 32.3893
3 *140:8 *360:D 14.7464
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *141 0.00855773
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *361:D I *D sky130_fd_sc_hd__dfbbn_2
*I *376:D I *D sky130_fd_sc_hd__dfrtp_4
*I *413:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *361:D 0
2 *376:D 0.000553559
3 *413:X 0.00165227
4 *141:16 0.00220583
5 *376:D *364:D 0.000174702
6 *376:D *143:10 5.04829e-06
7 *364:RESET_B *141:16 0.000601934
8 *364:SET_B *376:D 7.60548e-05
9 *366:RESET_B *141:16 0.000180295
10 *376:CLK *376:D 5.04829e-06
11 *389:A *141:16 2.99747e-05
12 *5:29 *376:D 0.000689683
13 *5:29 *141:16 8.50222e-05
14 *9:14 *141:16 3.39313e-06
15 *10:7 *376:D 0.000212554
16 *10:7 *141:16 0.000181527
17 *33:18 *141:16 0.0011019
18 *96:68 *376:D 7.78924e-05
19 *116:39 *141:16 0.000721045
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *413:X *141:16 40.3714
2 *141:16 *376:D 27.05
3 *141:16 *361:D 13.8
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *142 0.00267151
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *366:D I *D sky130_fd_sc_hd__dfbbn_2
*I *375:D I *D sky130_fd_sc_hd__dfrtp_4
*I *414:X O *D sky130_fd_sc_hd__dlygate4sd3_1
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *366:D 0.00032073
2 *375:D 0.000119413
3 *414:X 0.00029341
4 *142:10 0.000733553
5 *366:D *164:16 3.55007e-05
6 *364:SET_B *142:10 0.00016553
7 *375:CLK *366:D 0.000442556
8 *375:CLK *375:D 0.000167934
9 *375:RESET_B *366:D 1.99581e-05
10 *6:19 *142:10 0.000133034
11 *129:15 *366:D 0.000145269
12 *129:15 *375:D 9.46172e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *414:X *142:10 24.0321
2 *142:10 *375:D 12.7107
3 *142:10 *366:D 17.1036
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *143 0.00239154
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *364:D I *D sky130_fd_sc_hd__dfbbn_2
*I *377:D I *D sky130_fd_sc_hd__dfrtp_4
*I *415:X O *D sky130_fd_sc_hd__dlygate4sd3_1
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *364:D 0.000147894
2 *377:D 5.21751e-05
3 *415:X 0.000502138
4 *143:10 0.000702207
5 *143:10 *415:A 2.58616e-05
6 *364:SET_B *143:10 6.06556e-06
7 *374:D *364:D 2.16355e-05
8 *376:D *364:D 0.000174702
9 *376:D *143:10 5.04829e-06
10 *376:RESET_B *143:10 7.67734e-06
11 *5:29 *364:D 1.36494e-05
12 *5:29 *377:D 7.53109e-05
13 *5:29 *143:10 2.75989e-05
14 *10:7 *364:D 0.000227128
15 *10:7 *377:D 0.000103468
16 *11:17 *143:10 0.000298979
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *415:X *143:10 19.6661
2 *143:10 *377:D 15.2911
3 *143:10 *364:D 17.6482
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *144 0.0011152
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *369:D I *D sky130_fd_sc_hd__dfbbn_2
*I *416:X O *D sky130_fd_sc_hd__dlygate4sd3_1
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *369:D 0.000281958
2 *416:X 0.000281958
3 *369:D *386:D 0.000150434
4 *369:D *162:8 6.65668e-05
5 *322:A *369:D 6.36477e-05
6 *369:SET_B *369:D 1.13359e-05
7 *34:16 *369:D 9.80426e-05
8 *100:22 *369:D 0.000161252
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *416:X *369:D 33.6
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *145 0.0120064
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *373:D I *D sky130_fd_sc_hd__dfrtp_4
*I *423:X O *D sky130_fd_sc_hd__buf_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *373:D 0.000760691
2 *423:X 0.000764244
3 *145:28 0.00230427
4 *145:17 0.00230782
5 *373:D *412:A 2.41274e-06
6 *145:17 *424:A 0.000224573
7 *145:17 *439:A 0.000366794
8 *145:17 *442:A 4.63588e-05
9 *145:17 *153:10 0.000186759
10 *145:28 *362:D 0.000409699
11 *145:28 *367:D 0.00012108
12 *145:28 *382:D 0.000130702
13 pad_gpio_ana_pol *145:17 5.44807e-05
14 pad_gpio_dm[1] *145:28 4.71956e-05
15 *184:DIODE *145:17 0.000146158
16 *326:A *145:28 0.000246428
17 *360:SET_B *145:28 4.99584e-05
18 *364:RESET_B *145:28 3.16356e-05
19 *367:CLK_N *145:28 7.17478e-05
20 *368:CLK_N *145:28 0.000246085
21 *368:D *145:28 1.88563e-05
22 *372:RESET_B *145:28 0.000143175
23 *372:SET_B *145:28 0.000476565
24 *373:RESET_B *373:D 0.000251507
25 *373:RESET_B *145:28 0.000201656
26 *383:D *145:28 0.000154819
27 *385:D *145:28 4.54854e-05
28 *2:21 *145:28 0.00015409
29 *3:22 *145:28 0.000206598
30 *35:13 *145:17 0.000261968
31 *51:17 *145:28 0.000200635
32 *99:14 *145:28 0.00058242
33 *106:29 *145:28 7.26018e-05
34 *117:39 *373:D 3.38116e-06
35 *119:29 *145:17 0.000607811
36 *126:10 *373:D 0.000105778
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *423:X *145:17 43.1929
2 *145:17 *145:28 46.8571
3 *145:28 *373:D 22.1571
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *146 0.0026494
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *372:D I *D sky130_fd_sc_hd__dfbbn_2
*I *381:D I *D sky130_fd_sc_hd__dfrtp_4
*I *417:X O *D sky130_fd_sc_hd__dlygate4sd3_1
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *372:D 0
2 *381:D 0.000421249
3 *417:X 0.000251515
4 *146:11 0.000672764
5 *146:11 *417:A 0.00010872
6 *146:11 *158:46 2.41274e-06
7 *146:11 *158:70 1.82679e-05
8 *344:A *381:D 0.000107496
9 *349:A *146:11 3.82228e-05
10 *370:SET_B *381:D 0.000117562
11 *381:RESET_B *381:D 0.000127368
12 *388:A *146:11 6.3657e-05
13 *428:A *146:11 0.000126618
14 *11:33 *381:D 4.9e-05
15 *97:19 *381:D 5.71849e-05
16 *115:20 *381:D 2.02993e-05
17 *132:6 *381:D 0.000155293
18 *132:6 *146:11 0.000311769
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *417:X *146:11 24.1571
2 *146:11 *381:D 27.2464
3 *146:11 *372:D 9.3
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *147 0.00187844
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *380:D I *D sky130_fd_sc_hd__dfrtp_4
*I *371:D I *D sky130_fd_sc_hd__dfbbn_2
*I *418:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *380:D 2.52522e-05
2 *371:D 0.000209824
3 *418:X 0.000157146
4 *147:8 0.000392222
5 *371:D *370:D 9.74796e-05
6 *147:8 *158:46 0.000156076
7 *365:SET_B *371:D 0.000396928
8 *365:SET_B *147:8 8.96342e-05
9 *371:SET_B *371:D 3.82228e-05
10 *403:A *380:D 5.20546e-06
11 *32:43 *380:D 6.08467e-05
12 *111:8 *371:D 0.000164976
13 *111:8 *147:8 8.46261e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *418:X *147:8 16.4964
2 *147:8 *371:D 20.0321
3 *147:8 *380:D 14.3357
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *148 0.00418462
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *384:D I *D sky130_fd_sc_hd__dfrtp_4
*I *367:D I *D sky130_fd_sc_hd__dfbbn_2
*I *407:X O *D sky130_fd_sc_hd__dlygate4sd3_1
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *384:D 0.000692089
2 *367:D 0.000428687
3 *407:X 0
4 *148:4 0.00112078
5 *367:D *153:10 2.60476e-05
6 *384:D *312:A 8.87724e-05
7 *323:A_N *384:D 5.46207e-05
8 *367:SET_B *384:D 7.26748e-05
9 *372:RESET_B *367:D 0.000143175
10 *383:RESET_B *384:D 9.37259e-05
11 *384:RESET_B *384:D 9.33587e-05
12 *32:43 *367:D 1.43229e-05
13 *41:33 *384:D 0
14 *54:16 *384:D 2.77543e-05
15 *106:29 *367:D 0.000430405
16 *106:29 *384:D 0
17 *120:18 *384:D 0.000471811
18 *120:58 *384:D 0.000169659
19 *138:10 *384:D 0.000135664
20 *145:28 *367:D 0.00012108
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *407:X *148:4 9.3
2 *148:4 *367:D 26.8893
3 *148:4 *384:D 33.1616
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *149 0.00503726
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *379:D I *D sky130_fd_sc_hd__dfrtp_4
*I *370:D I *D sky130_fd_sc_hd__dfbbn_2
*I *408:X O *D sky130_fd_sc_hd__dlygate4sd3_1
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *379:D 0.000564771
2 *370:D 0.000463472
3 *408:X 4.51842e-05
4 *149:7 0.00107343
5 *365:SET_B *370:D 0.000106132
6 *371:D *370:D 9.74796e-05
7 *41:33 *379:D 9.55802e-05
8 *97:36 *149:7 6.08467e-05
9 *111:8 *370:D 0.000366928
10 *111:8 *379:D 0.000552468
11 *114:55 *370:D 1.41307e-05
12 *119:29 *370:D 6.54273e-05
13 *137:13 *370:D 0.000985958
14 *137:13 *379:D 0.000545452
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *408:X *149:7 14.3357
2 *149:7 *370:D 28.3357
3 *149:7 *379:D 25.4607
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *150 0.00188137
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *382:D I *D sky130_fd_sc_hd__dfrtp_4
*I *362:D I *D sky130_fd_sc_hd__dfbbn_2
*I *409:X O *D sky130_fd_sc_hd__dlygate4sd3_1
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *382:D 0.000169709
2 *362:D 0.000242231
3 *409:X 0
4 *150:5 0.00041194
5 *368:CLK_N *362:D 1.03594e-05
6 *368:CLK_N *382:D 0.000141062
7 *54:16 *382:D 0.000138356
8 *106:29 *362:D 0.000115333
9 *110:17 *382:D 0.000111974
10 *145:28 *362:D 0.000409699
11 *145:28 *382:D 0.000130702
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *409:X *150:5 13.8
2 *150:5 *362:D 19.925
3 *150:5 *382:D 18.7464
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *151 0.00390945
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *378:D I *D sky130_fd_sc_hd__dfrtp_4
*I *365:D I *D sky130_fd_sc_hd__dfbbn_2
*I *410:X O *D sky130_fd_sc_hd__dlygate4sd3_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *378:D 0.000952047
2 *365:D 1.79621e-05
3 *410:X 0.000508651
4 *151:8 0.00147866
5 *378:D *408:A 5.20546e-06
6 *378:D *157:28 9.51758e-06
7 *378:CLK *378:D 0.000325455
8 *10:20 *365:D 5.46907e-05
9 *10:20 *151:8 6.1664e-05
10 *41:33 *151:8 0.000374343
11 *137:13 *365:D 5.46907e-05
12 *137:13 *151:8 6.65668e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *410:X *151:8 20.3
2 *151:8 *365:D 14.5321
3 *151:8 *378:D 24.2509
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
*END
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *152 0.00238569
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *436:A I *D sky130_fd_sc_hd__buf_16
*I *370:Q O *D sky130_fd_sc_hd__dfbbn_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *436:A 0.000811987
2 *370:Q 0.000811987
3 *436:A *438:A 0.000228941
4 *436:A *442:A 6.27782e-05
5 *198:DIODE *436:A 6.46815e-05
6 *339:B *436:A 0.000157107
7 *4:21 *436:A 0.000161626
8 *119:29 *436:A 8.65796e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *370:Q *436:A 42.7429
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *153 0.00326427
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *437:A I *D sky130_fd_sc_hd__buf_16
*I *372:Q O *D sky130_fd_sc_hd__dfbbn_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *437:A 0
2 *372:Q 0.00114994
3 *153:10 0.00114994
4 *323:A_N *153:10 4.15414e-05
5 *367:D *153:10 2.60476e-05
6 *367:SET_B *153:10 0.000400271
7 *431:A *153:10 3.21368e-06
8 *24:9 *153:10 3.26102e-05
9 *32:43 *153:10 4.57372e-05
10 *98:17 *153:10 0.000228215
11 *106:29 *153:10 0
12 *145:17 *153:10 0.000186759
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *372:Q *153:10 40.8714
2 *153:10 *437:A 9.3
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *154 0.00229049
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *438:A I *D sky130_fd_sc_hd__buf_16
*I *371:Q O *D sky130_fd_sc_hd__dfbbn_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *438:A 0.000499605
2 *371:Q 0.000499605
3 *198:DIODE *438:A 2.39545e-05
4 *436:A *438:A 0.000228941
5 *3:27 *438:A 0.00032603
6 *3:33 *438:A 0.000285475
7 *4:21 *438:A 0.000313144
8 *11:58 *438:A 0.000113739
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *371:Q *438:A 40.2429
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *155 0.0034326
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *439:A I *D sky130_fd_sc_hd__buf_16
*I *367:Q O *D sky130_fd_sc_hd__dfbbn_2
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *439:A 0.000665119
2 *367:Q 0.000665119
3 pad_gpio_dm[0] *439:A 4.24488e-05
4 *184:DIODE *439:A 0.000250343
5 *341:A_N *439:A 3.34603e-05
6 *341:B *439:A 0.000111352
7 *367:RESET_B *439:A 0.000110949
8 *388:A *439:A 0.000441308
9 *400:A *439:A 1.07549e-05
10 *431:A *439:A 0.000402381
11 *24:9 *439:A 5.35029e-05
12 *119:29 *439:A 4.19841e-05
13 *121:7 *439:A 1.56911e-05
14 *121:8 *439:A 0.000177473
15 *121:36 *439:A 4.39194e-05
16 *145:17 *439:A 0.000366794
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *367:Q *439:A 45.7964
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *156 0.00212001
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *424:A I *D sky130_fd_sc_hd__buf_16
*I *395:HI O *D sky130_fd_sc_hd__conb_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *424:A 0.000507498
2 *395:HI 0.000507498
3 *424:A *442:A 7.17116e-05
4 pad_gpio_ana_pol *424:A 0.000808733
5 *145:17 *424:A 0.000224573
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *395:HI *424:A 30.6536
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *157 0.0153886
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *373:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *383:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *385:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *384:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *382:CLK I *D sky130_fd_sc_hd__dfrtp_4
*I *440:A I *D sky130_fd_sc_hd__clkbuf_16
*I *393:X O *D sky130_fd_sc_hd__clkbuf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *373:CLK 0.000600053
2 *383:CLK 0.000178656
3 *385:CLK 0.00015868
4 *384:CLK 0.000913377
5 *382:CLK 1.69677e-05
6 *440:A 0.000745353
7 *393:X 4.51842e-05
8 *157:40 0.00120765
9 *157:31 0.000350579
10 *157:28 0.00155812
11 *157:21 0.00186166
12 *157:7 0.000870689
13 *384:CLK *312:A 3.6276e-06
14 *385:CLK *411:A 0.000124044
15 *157:40 *411:A 2.91326e-05
16 *186:DIODE *440:A 0.000163168
17 *204:DIODE *440:A 0.000630419
18 *323:A_N *384:CLK 5.01846e-05
19 *326:A *384:CLK 1.40736e-05
20 *340:B *385:CLK 5.04829e-06
21 *342:B *440:A 5.14448e-05
22 *344:B *157:31 3.07796e-05
23 *349:A *157:31 0.000224425
24 *365:CLK_N *373:CLK 5.4704e-05
25 *365:CLK_N *440:A 0.000231561
26 *365:CLK_N *157:21 0.000173028
27 *365:RESET_B *157:28 2.16355e-05
28 *370:CLK_N *440:A 0.000113237
29 *370:SET_B *157:7 6.08467e-05
30 *371:CLK_N *440:A 0.000378093
31 *374:D *385:CLK 9.62217e-06
32 *375:CLK *373:CLK 0.000143161
33 *376:RESET_B *384:CLK 6.11872e-05
34 *378:D *157:28 9.51758e-06
35 *384:RESET_B *384:CLK 0.000259643
36 *392:A *440:A 0.000257331
37 *396:A *385:CLK 0.00030765
38 *396:A *157:31 0.000329444
39 *396:A *157:40 0.000205234
40 *397:A *383:CLK 1.54322e-05
41 *399:A *384:CLK 6.11447e-06
42 *428:A *157:28 1.8254e-05
43 *1:23 *373:CLK 1.66771e-05
44 *3:22 *157:31 5.65111e-05
45 *3:22 *157:40 6.7262e-05
46 *5:29 *440:A 1.75024e-05
47 *8:11 *373:CLK 4.64001e-05
48 *8:19 *373:CLK 9.17798e-05
49 *9:14 *373:CLK 0.00100289
50 *9:37 *440:A 1.13142e-05
51 *34:16 *384:CLK 3.76053e-05
52 *54:16 *382:CLK 2.57986e-05
53 *95:8 *373:CLK 0.000178277
54 *95:8 *440:A 0.000141811
55 *95:8 *157:21 0.000176793
56 *96:68 *373:CLK 0.000221977
57 *106:13 *385:CLK 1.88422e-05
58 *110:17 *382:CLK 2.57986e-05
59 *114:8 *385:CLK 0.000107496
60 *114:55 *440:A 0.000119789
61 *114:83 *440:A 0.000312422
62 *115:5 *383:CLK 1.82679e-05
63 *115:5 *157:28 9.94284e-06
64 *115:14 *157:28 2.61033e-05
65 *120:61 *384:CLK 0.000107496
66 *126:10 *373:CLK 6.08467e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *393:X *157:7 14.3357
2 *157:7 *440:A 34.1571
3 *157:7 *157:21 2.55357
4 *157:21 *157:28 16.6786
5 *157:28 *157:31 10.0893
6 *157:31 *382:CLK 14.3357
7 *157:31 *157:40 3.16071
8 *157:40 *384:CLK 33.1036
9 *157:40 *385:CLK 17.925
10 *157:28 *383:CLK 11.9071
11 *157:21 *373:CLK 29.6393
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *158 0.0187412
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *355:A I *D sky130_fd_sc_hd__inv_2
*I *312:A I *D sky130_fd_sc_hd__inv_2
*I *356:A I *D sky130_fd_sc_hd__inv_2
*I *441:A I *D sky130_fd_sc_hd__clkbuf_16
*I *351:A I *D sky130_fd_sc_hd__inv_2
*I *350:A I *D sky130_fd_sc_hd__inv_2
*I *348:A I *D sky130_fd_sc_hd__inv_2
*I *353:A I *D sky130_fd_sc_hd__inv_2
*I *394:X O *D sky130_fd_sc_hd__clkbuf_16
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *355:A 0
2 *312:A 0.000813228
3 *356:A 0
4 *441:A 0.000661222
5 *351:A 5.8898e-05
6 *350:A 0
7 *348:A 0
8 *353:A 0
9 *394:X 0
10 *158:70 0.00154235
11 *158:51 0.00112082
12 *158:46 0.00213874
13 *158:24 0.000334431
14 *158:17 0.000454325
15 *158:10 0.000428048
16 *158:4 0.00119928
17 *158:46 *408:A 3.02249e-05
18 *158:46 *418:A 6.74812e-05
19 *158:70 *409:A 0.000311913
20 *173:DIODE *158:17 0.000126335
21 *201:DIODE *441:A 0.000205404
22 *209:DIODE *158:10 8.21761e-06
23 *327:A_N *312:A 4.31603e-06
24 *329:A_N *312:A 1.58551e-05
25 *349:A *158:46 9.80242e-07
26 *349:A *158:70 5.429e-05
27 *352:A *158:10 1.37566e-05
28 *357:A *441:A 0.000161817
29 *357:A *158:51 0.000387111
30 *361:CLK_N *351:A 1.22289e-05
31 *361:CLK_N *158:24 0.000141399
32 *362:CLK_N *158:70 0.00028688
33 *363:CLK_N *158:70 0.000536223
34 *364:CLK_N *351:A 0.000176652
35 *364:CLK_N *158:24 0.000358287
36 *371:CLK_N *158:10 0.000210531
37 *371:CLK_N *158:46 0.000380352
38 *371:RESET_B *158:70 0.000186579
39 *372:CLK_N *158:46 0.000101887
40 *383:D *158:70 0.000253215
41 *384:CLK *312:A 3.6276e-06
42 *384:D *312:A 8.87724e-05
43 *384:RESET_B *312:A 8.35355e-06
44 *4:21 *158:70 0.000248457
45 *9:35 *158:46 0.000407526
46 *39:10 *441:A 6.88361e-05
47 *41:33 *158:70 9.95234e-05
48 *54:16 *312:A 0
49 *97:19 *158:51 0.000650015
50 *97:24 *158:46 1.25805e-05
51 *97:36 *158:10 0.000104653
52 *97:36 *158:46 0.000823384
53 *106:29 *312:A 0.000289166
54 *116:48 *351:A 0.00021661
55 *116:48 *158:24 0.000496078
56 *116:53 *158:10 0.000252128
57 *116:53 *158:17 0.000549196
58 *116:53 *158:24 0.000263436
59 *120:61 *312:A 8.58641e-05
60 *129:15 *158:10 3.44412e-06
61 *129:15 *158:17 0.000132509
62 *129:15 *158:24 2.50929e-05
63 *132:6 *158:51 0.00095192
64 *146:11 *158:46 2.41274e-06
65 *146:11 *158:70 1.82679e-05
66 *147:8 *158:46 0.000156076
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *394:X *158:4 9.3
2 *158:4 *158:10 11.0893
3 *158:10 *353:A 13.8
4 *158:10 *158:17 7.10714
5 *158:17 *348:A 13.8
6 *158:17 *158:24 9.83929
7 *158:24 *350:A 13.8
8 *158:24 *351:A 16.6571
9 *158:4 *158:46 18.4821
10 *158:46 *158:51 23.0893
11 *158:51 *441:A 20.5321
12 *158:51 *356:A 9.3
13 *158:46 *158:70 24.9643
14 *158:70 *312:A 30.7643
15 *158:70 *355:A 9.3
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *159 0.0011949
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *412:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *373:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *412:A 0.000392327
2 *373:Q 0.000392327
3 *412:A *164:16 1.07549e-05
4 *322:B *412:A 6.71638e-05
5 *360:CLK_N *412:A 8.4946e-05
6 *360:D *412:A 0.000110306
7 *373:D *412:A 2.41274e-06
8 *427:A *412:A 0.000134662
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *373:Q *412:A 34.9036
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *160 0.000862718
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *407:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *383:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *407:A 0.000128694
2 *383:Q 0.000128694
3 *13:66 *407:A 0.000137252
4 *54:16 *407:A 0.000140383
5 *67:10 *407:A 0.00031441
6 *121:36 *407:A 1.32845e-05
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *383:Q *407:A 31.975
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *161 0.000899789
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *411:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *384:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *411:A 0.000216223
2 *384:Q 0.000216223
3 *374:D *411:A 3.12402e-05
4 *385:CLK *411:A 0.000124044
5 *3:22 *411:A 0.000282925
6 *157:40 *411:A 2.91326e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *384:Q *411:A 31.975
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *162 0.00772466
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *416:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *386:D I *D sky130_fd_sc_hd__dfrtp_2
*I *385:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *416:A 0.000395366
2 *386:D 0.0021838
3 *385:Q 0.000316313
4 *162:8 0.00289548
5 *322:A *386:D 0.000261379
6 *361:CLK_N *386:D 0.000145255
7 *361:RESET_B *386:D 6.26025e-05
8 *369:CLK_N *386:D 5.24474e-05
9 *369:D *386:D 0.000150434
10 *369:D *162:8 6.65668e-05
11 *369:RESET_B *416:A 2.41274e-06
12 *369:SET_B *162:8 8.35027e-05
13 *399:A *162:8 0.000124362
14 *33:18 *416:A 0.000112897
15 *34:16 *386:D 1.56833e-05
16 *34:16 *162:8 1.26994e-05
17 *42:10 *416:A 0.000112897
18 *67:10 *162:8 0.000198119
19 *104:7 *386:D 0.000442865
20 *137:13 *386:D 8.95662e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *385:Q *162:8 24.8
2 *162:8 *386:D 35.0946
3 *162:8 *416:A 23.3536
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *163 0.000959483
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *414:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *374:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *414:A 0.000185194
2 *374:Q 0.000185194
3 *183:DIODE *414:A 0.000253345
4 *364:CLK_N *414:A 0.000100956
5 *364:SET_B *414:A 4.47179e-05
6 *7:11 *414:A 0.000138453
7 *94:8 *414:A 5.1623e-05
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *374:Q *414:A 32.6714
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *164 0.00699943
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *413:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *375:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *413:A 0.000261789
2 *375:Q 0.00177552
3 *164:16 0.0020373
4 *366:D *164:16 3.55007e-05
5 *366:RESET_B *164:16 0.000127809
6 *373:RESET_B *164:16 0.000537864
7 *412:A *164:16 1.07549e-05
8 *427:A *164:16 0.000253078
9 *4:9 *164:16 0.000309515
10 *30:8 *413:A 0.000919373
11 *33:18 *413:A 0.000473045
12 *109:11 *413:A 0.000216458
13 *129:15 *164:16 4.14268e-05
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *375:Q *164:16 41.5143
2 *164:16 *413:A 20.1036
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *165 0.000621978
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *415:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *376:Q O *D sky130_fd_sc_hd__dfrtp_4
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *415:A 0.00011814
2 *376:Q 0.00011814
3 *376:RESET_B *415:A 0.000359836
4 *143:10 *415:A 2.58616e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *376:Q *415:A 21.6
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *166 0.000489087
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *410:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *377:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *410:A 8.92302e-05
2 *377:Q 8.92302e-05
3 *363:CLK_N *410:A 6.08467e-05
4 *365:RESET_B *410:A 0.00013697
5 *11:17 *410:A 4.9e-05
6 *41:33 *410:A 2.58616e-05
7 *114:15 *410:A 1.03594e-05
8 *132:6 *410:A 2.75892e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *377:Q *410:A 30.0821
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *167 0.00128501
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *408:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *378:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *408:A 0.000247594
2 *378:Q 0.000247594
3 *378:D *408:A 5.20546e-06
4 *8:19 *408:A 0.000298287
5 *95:8 *408:A 0.000291452
6 *97:36 *408:A 0.000164656
7 *158:46 *408:A 3.02249e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *378:Q *408:A 34.2964
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *168 0.00186317
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *418:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *379:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *418:A 0.000326248
2 *379:Q 0.000326248
3 *363:CLK_N *418:A 4.23858e-05
4 *366:SET_B *418:A 2.28034e-05
5 *370:SET_B *418:A 0.00013832
6 *372:CLK_N *418:A 0.000161243
7 *379:RESET_B *418:A 0.000129518
8 *34:21 *418:A 0.000538614
9 *41:33 *418:A 0.000110306
10 *158:46 *418:A 6.74812e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *379:Q *418:A 37.3143
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *169 0.000775235
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *417:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *380:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *417:A 0.000185724
2 *380:Q 0.000185724
3 *388:A *417:A 8.69237e-05
4 *388:TE_B *417:A 4.2372e-05
5 *428:A *417:A 0.000147742
6 *132:6 *417:A 1.80303e-05
7 *146:11 *417:A 0.00010872
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *380:Q *417:A 31.6179
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *170 0.00143017
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *409:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *381:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *409:A 0.000284962
2 *381:Q 0.000284962
3 *344:A *409:A 7.54269e-06
4 *344:B *409:A 0.000111802
5 *362:CLK_N *409:A 0.000109427
6 *4:21 *409:A 0.000319562
7 *158:70 *409:A 0.000311913
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *381:Q *409:A 34.1536
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *171 0.000935138
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *406:A I *D sky130_fd_sc_hd__dlygate4sd3_1
*I *382:Q O *D sky130_fd_sc_hd__dfrtp_4
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *406:A 0.000282937
2 *382:Q 0.000282937
3 *120:7 *406:A 0.00015888
4 *121:51 *406:A 0.000154145
5 *138:10 *406:A 5.6238e-05
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *382:Q *406:A 23.6536
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*END
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*D_NET *172 0.00249831
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CONN
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
*I *442:A I *D sky130_fd_sc_hd__buf_16
*I *395:LO O *D sky130_fd_sc_hd__conb_1
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
*CAP
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *442:A 0.000696457
2 *395:LO 0.000696457
3 *195:DIODE *442:A 0.000606218
4 *198:DIODE *442:A 0.000318331
5 *424:A *442:A 7.17116e-05
6 *436:A *442:A 6.27782e-05
7 *145:17 *442:A 4.63588e-05
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
*RES
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
1 *395:LO *442:A 41.0107
[DATA] Add spef/sdf views
2021-11-28 07:28:59 -06:00
*END