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caravel/verilog/rtl/caravan_netlists.v

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Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`timescale 1 ns / 1 ps
`define UNIT_DELAY #1
`define USE_POWER_PINS
`ifdef SIM
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "defines.v"
`include "user_defines.v"
`include "pads.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
`ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
`include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
A number of changes to the caravan netlists, (1) to correct for problems that had been fixed recently in caravel, and which cause the caravan testbench to break, but which were not noticed; (2) corrected the count of gpio_control_block modules, which was one off, with two of them overlapping (not sure how that even passes simulation, but it did); (3) fixed a power connection in the caravel chip_io, which should have caused chip_io to fail LVS, so apparently LVS was not run on chip_io. . .
2021-11-22 08:46:21 -06:00
`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`else
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
A number of changes to the caravan netlists, (1) to correct for problems that had been fixed recently in caravel, and which cause the caravan testbench to break, but which were not noticed; (2) corrected the count of gpio_control_block modules, which was one off, with two of them overlapping (not sure how that even passes simulation, but it did); (3) fixed a power connection in the caravel chip_io, which should have caused chip_io to fail LVS, so apparently LVS was not run on chip_io. . .
2021-11-22 08:46:21 -06:00
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire
// definitions
`default_nettype wire
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/digital_pll.v"
Modified all of the Makefiles to better handle the GL netlist simulations, which is now done through setting an environment variable to point to the location of the management SoC wrapper. Added the missing user project wrappers to the GL directory (copied from the original caravel repository), and also the GL version of chip_io_alt. Modified the caravan_netlists and caravel_netlists files to import the correct list of gate level netlists, which has been reduced by moving "include" statements for components of the management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 16:13:53 -06:00
`include "gl/caravel_clocking.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/user_id_programming.v"
`include "gl/chip_io_alt.v"
Modified all of the Makefiles to better handle the GL netlist simulations, which is now done through setting an environment variable to point to the location of the management SoC wrapper. Added the missing user project wrappers to the GL directory (copied from the original caravel repository), and also the GL version of chip_io_alt. Modified the caravan_netlists and caravel_netlists files to import the correct list of gate level netlists, which has been reduced by moving "include" statements for components of the management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 16:13:53 -06:00
`include "gl/housekeeping.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/mprj_logic_high.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/mprj2_logic_high.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/mgmt_protect.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/mgmt_protect_hv.v"
Modified the GPIO control block to buffer the constant high/low outputs. Corrected the pad constant connections to all be in the correct domain (1.8V or 3.3V). Created a new "constant_block" module that generates a single constant 1 and 0 value in the 1.8V domain, and used 7 of these in the chip_io (and chip_io_alt) modules to create the 1.8V domain constant signals for the seven pads belonging to the management (clock, reset, flash SPI, and management GPIO).
2022-09-20 16:49:08 -05:00
`include "gl/constant_block.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/gpio_control_block.v"
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`include "gl/gpio_defaults_block.v"
Modified all of the Makefiles to better handle the GL netlist simulations, which is now done through setting an environment variable to point to the location of the management SoC wrapper. Added the missing user project wrappers to the GL directory (copied from the original caravel repository), and also the GL version of chip_io_alt. Modified the caravan_netlists and caravel_netlists files to import the correct list of gate level netlists, which has been reduced by moving "include" statements for components of the management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 16:13:53 -06:00
`include "gl/gpio_defaults_block_0403.v"
`include "gl/gpio_defaults_block_1803.v"
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
`include "gl/gpio_defaults_block_0801.v"
Added buffers to the top level, inside a macro called gpio_signal_buffering (gpio_signal_buffering_alt in caravan). Note that this macro requires manual placement and routing, like the padframe, and the top level will need to route around its own internal routes.
2022-10-13 12:29:27 -05:00
`include "gl/gpio_signal_buffering_alt.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/gpio_logic_high.v"
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 20:43:09 -05:00
`include "gl/xres_buf.v"
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 08:23:22 -06:00
`include "gl/spare_logic_block.v"
Added a reference to the new file "gl/mgmt_defines.v" in the caravel_pico repository. The issue is that each SoC implementation defines its own modules and therefore needs its own includes. The implication is that this file now needs to exist in every SoC implementation's verilog/gl/ directory.
2021-12-24 10:46:34 -06:00
`include "gl/mgmt_defines.v"
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 08:23:22 -06:00
`include "gl/mgmt_core_wrapper.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/caravan.v"
`else
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "digital_pll.v"
Corrected an inadvertant error in caravel_netlists.v that prevents gate-level simulations from running. Corrected caravan_netlists.v, which did not have the same change made yesterday to caravel_netlists.v for the DLL.
2021-12-07 08:14:59 -06:00
`include "digital_pll_controller.v"
`include "ring_osc2x13.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "caravel_clocking.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "user_id_programming.v"
`include "clock_div.v"
`include "mprj_io.v"
`include "chip_io_alt.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "housekeeping_spi.v"
`include "housekeeping.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "mprj_logic_high.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mprj2_logic_high.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "mgmt_protect.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mgmt_protect_hv.v"
Modified the GPIO control block to buffer the constant high/low outputs. Corrected the pad constant connections to all be in the correct domain (1.8V or 3.3V). Created a new "constant_block" module that generates a single constant 1 and 0 value in the 1.8V domain, and used 7 of these in the chip_io (and chip_io_alt) modules to create the 1.8V domain constant signals for the seven pads belonging to the management (clock, reset, flash SPI, and management GPIO).
2022-09-20 16:49:08 -05:00
`include "constant_block.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gpio_control_block.v"
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`include "gpio_defaults_block.v"
Added buffers to the top level, inside a macro called gpio_signal_buffering (gpio_signal_buffering_alt in caravan). Note that this macro requires manual placement and routing, like the padframe, and the top level will need to route around its own internal routes.
2022-10-13 12:29:27 -05:00
`include "gpio_signal_buffering_alt.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gpio_logic_high.v"
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 20:43:09 -05:00
`include "xres_buf.v"
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 08:23:22 -06:00
`include "spare_logic_block.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mgmt_core_wrapper.v"
`include "caravan.v"
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "simple_por.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif