gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V). Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
caravel_pico repository. The issue is that each SoC implementation
defines its own modules and therefore needs its own includes. The
implication is that this file now needs to exist in every SoC
implementation's verilog/gl/ directory.
gate-level simulations from running. Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
which is now done through setting an environment variable to point to the
location of the management SoC wrapper. Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt. Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
problems that had been fixed recently in caravel, and which cause
the caravan testbench to break, but which were not noticed; (2)
corrected the count of gpio_control_block modules, which was one
off, with two of them overlapping (not sure how that even passes
simulation, but it did); (3) fixed a power connection in the
caravel chip_io, which should have caused chip_io to fail LVS,
so apparently LVS was not run on chip_io. . .
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
Tim Edwards