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caravel/verilog/rtl/caravan_netlists.v

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Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`timescale 1 ns / 1 ps
`define UNIT_DELAY #1
`define USE_POWER_PINS
`ifdef SIM
Updated the caravan netlist and implemented the caravan testbench.
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`include "defines.v"
`include "user_defines.v"
`include "pads.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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Updated the caravan netlist and implemented the caravan testbench.
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/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
`ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
`include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
A number of changes to the caravan netlists, (1) to correct for problems that had been fixed recently in caravel, and which cause the caravan testbench to break, but which were not noticed; (2) corrected the count of gpio_control_block modules, which was one off, with two of them overlapping (not sure how that even passes simulation, but it did); (3) fixed a power connection in the caravel chip_io, which should have caused chip_io to fail LVS, so apparently LVS was not run on chip_io. . .
2021-11-22 08:46:21 -06:00
`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`else
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
A number of changes to the caravan netlists, (1) to correct for problems that had been fixed recently in caravel, and which cause the caravan testbench to break, but which were not noticed; (2) corrected the count of gpio_control_block modules, which was one off, with two of them overlapping (not sure how that even passes simulation, but it did); (3) fixed a power connection in the caravel chip_io, which should have caused chip_io to fail LVS, so apparently LVS was not run on chip_io. . .
2021-11-22 08:46:21 -06:00
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire
// definitions
`default_nettype wire
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/mgmt_core.v"
`include "gl/digital_pll.v"
`include "gl/DFFRAM.v"
`include "gl/storage.v"
`include "gl/user_id_programming.v"
`include "gl/chip_io_alt.v"
`include "gl/mprj_logic_high.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/mprj2_logic_high.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "gl/mgmt_protect.v"
Updated the caravan netlist and implemented the caravan testbench.
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`include "gl/mgmt_protect_hv.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gl/gpio_control_block.v"
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`include "gl/gpio_defaults_block.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/gpio_logic_high.v"
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 20:43:09 -05:00
`include "gl/xres_buf.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "gl/caravan.v"
`else
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "digital_pll.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "caravel_clocking.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`include "user_id_programming.v"
`include "clock_div.v"
`include "mprj_io.v"
`include "chip_io_alt.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "housekeeping_spi.v"
`include "housekeeping.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "mprj_logic_high.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mprj2_logic_high.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "mgmt_protect.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mgmt_protect_hv.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gpio_control_block.v"
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`include "gpio_defaults_block.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`include "gpio_logic_high.v"
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 20:43:09 -05:00
`include "xres_buf.v"
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "mgmt_core_wrapper.v"
`include "caravan.v"
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 14:08:13 -05:00
`include "simple_por.v"
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif